A PENNWELL PUBLICATION: DECEMBER 1992

COMPUTER

Data I/O's Tom Clark on:

FPGA design FOR ELECTRONIC ENGINEERS & ENGINEERING MANAGERS

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CIRCLE NO. 1

Innovative Technology In System Packaging

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CIRCLE NO. 2

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CIRCLE NO. 3

A PENNWELL PUBLICATION VOL 31, NO 12 / DECEMBER 1992

COMPUTER ‘Technology

and Design Directions

FOR ELECTRONIC ENGINEERS & ENGINEERING MANAGERS

Designers of embedded systems can enjoy increased compute power, higher integration and high-level pro- gramming lan- guages if they wish for, and can use, 32- bit microcontrollers in their next-genera-

tion designs............ 91 Ecitorlaliesceecsc 22 Calendar ................ 24

Advertiser Index.....143

COMING NEXT MONTH

Verilog and VHDL

DSP development | tools |

Disk drive control- | lers and ICs C cross compilers

Networking

ENEWS BRIEFS

MIPS forges ahead . . . Chorus spreads microkernel-based UNIX

. . Benchmarks proposed for fuzzy logic . . . ViaLink helps QuickLogic cut FPGA prices . . . Vitesse prices GaAs ASICs to beat BICMOS... A kinder, gentler EDIF? . . . Modeling informa- tion comes online . . . PCI gets expansion connector . . . Stand- ards set for memory interface . . . 486 rivalry continues ATRPEASEHTECI ss cas eed ats evteresthis ts aetcserwraalsn uesnceanan tek aputons kegbinieownacase 10

ETECHNOLOGY DIRECTIONS

Integrated Circuits

New clock chips are analgesic for run-length headaches ............ 34 IEDIVI Ge LS TRIAVEINE ea seeuencstesvsss snesracesuneoeranediapeetaeasenueasmitassaee 40 Analog Devices courts designers with open architecture DSP ......46

Software & Development Tools Alliances to speed acceptance of fuzzy logic technology............. 52

Computers & Subsystems

HP debuts VME, realtime SOIUtIONS..............cccccesereceeeessteeeeseees 58

Image processing gets price-performance boost...............0:6600 62

CAE/CAD Tools

No agreement on best way to link digital and analog

SIMIC eM Stee tanta coy taser Sere tee, Se Rept Mec cee Aes eal 67

ASICs & ASIC Design Tools

EDA vendors push to boost top-down design productivity.......... 70

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CAE/CAD Design Tools Windows-based PCB tool suite boasts workstation

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Computers & Subsystems sje ACCESS.bus hardware released for industrial and sje COM MME Cla EMVIROMIMENIS veceoe-c.cde-seataeececestocerus sector eee cake 128 ie Intel beefs up Multibus line using 486 processors ................66+. 130

Press <Left> or <Space> at the line starting point. Page 123

CONTINUED ON PAGE 5 COMPUTER DESIGN

DECEMBER 1992 3

Seeking an affordable, high-performance development system? Our Lite’s at the end of the tunnel.

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| Supporting 683xx and 68HC16 families. Call for specific microprocessors.

CIRCLE NO. 4

COMPUTER Technology

rs: and Design

DESIGN Directions

CONTINUED FROM PAGE 3

Tom Clark on: FPGA design

Logic designers using field pro- grammable logic devices have two basic choices when | it comes to design methodology — | structural and be- HAVIOFALE ce, woth oetac: 31

| Look for

OEM

INTEGRATION next month, featuring secondary and mezzanine buses, backplanes and enclosures.

TECHNOLOGY & DESIGN REPORTS

FPGA vendors turn their attention to tools

In the face of stiff competition, FPGA vendors are enhancing proprietary tools, enlisting third-party support, adding text-

based entry methods, and backing standards.

STi sea eMC ERR IB ose oe sna vore oe senec tees ade? os unns dda spsicdessaexeecoseaies 75

| GUIs move OSs toward

object orientation

Computer graphics, originally meant to display data, is now the way users interact with systems. A new generation of operat-

ing systems with fully integrated GUIs is meeting the demands

of those who want to work with their systems in a real-world environment of objects and actions.

TOT VVHNCIIIS eer wee katt, <2 Fees oaten: eee Ree ee ea cce,.. MeN 85

COVER STORY

32-bit power and tools bring cheer

to embedded system designers

Because of their increased compute power, higher integration, extensive tool sets, and a desire for the friendliness provided by high-level languages, more designers are putting 32-bit micro- controllers on their wish lists for next-generation products.

= EXOT TUE sic 2 Ree dhe aie, hese eee. Wee 91

EDESIGN STRATEGIES

| Truck simulator integrates

off-the-shelf subsystems

| Adefense contractor saw an opportunity to create its first

commercial product, the TTI50 Truck Driving Simulator. SMT MO NN eres 62 SE ccs hc ote tac Mace asnaed eashdcahndamstwesse 105

EPRODUCT FOCUS

STD Bus CPUs focus on solutions

Unlike VME, which has Motorola supporting it, or Multibus Il, which is backed by Intel, STD Bus may suffer from not having

a major semiconductor manufacturer behind it. But in reality,

STD has a strong position as a low-cost workhorse bus for embedded control. — Jeffrey Child.........:..ccccccessceceesceeeneeees 115

ECOLUMN

_ MIXED-SIGNAL DESIGN — Stephan Ohr

“Design for X:" A new push for manufacturability, testability Fe)11.0 fh 731051] 9 nn ee el Oy a a 132

Page 85

Page 115

COMPUTER DESIGN DECEMBER 1992 5

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No logic analyzer is, for that matter.

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To get you started, the GPX provides more channels than cable TV. Up to 160, for instance, of 80 MHz state analysis, and 32 channels of 1 GHz timing or 160 channels of 200 MHz transitional timing. ea

In short, enough to handle the world’s fastest microprocessors. And with that kind of performance, you can easily track your system at clock rates well beyond 50 MHz, which allows you to locate complex

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Enter the TDS 640.

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ANALYZER IS GREAT FOR os: IT’S NOT NEARLY ENOUGH. *"""”

pulses, and excessive Clock jitter or skew. Put all that together with the power of the GPX and you have a remarkably effective solution. Cost effective, too. In fact, the GPX and TDS together sell for less than competing scope/logic analyzer combinations. And if you buy the pair between now and February 28, 1993,

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Test and Measurement

CIRCLE NO. 5

TODAY'S FAMILY VALUES ARE 3 VOLTS.

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CIRCLE NO. 6

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EWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS

MIPS forges ahead

Last month, mips Technologies (Mountain View, CA) announced the R4400, the latest 64-bit mips microprocessor. Designers experi- enced with the R4000 won’t have to make any changes in hardware or software when using the new R4400. The only differences are cache size, clock rate and a new write buffer. This buffer takes the output from a graphics loop and runs it in parallel with the next loop, resulting in a substantial in- crease in graphics performance.

Although the cache size on the R4400 is double that of its prede- cessor, a 20 percent shrink in pro- cess technology has returned that real estate, resulting in a die size no larger than the R4000. The clock rate has been raised to 75 MHz, with 67 MHz and 50 MHz for backward compatibility. Tran- sistor count went up by a million on the R4400, with the increase fundamentally in cache. On-chip primary cache has been doubled from an 8k/8k instruction/data cache to a 16k/16k cache on the R4400. The secondary is the same. The processor is available in 3.3- and 5-V versions.

How does this new chip fit into the emerging RISC PC world? Even when Intel’s P5 finally hits the streets, the MIPS crowd already has the more powerful R4000— and the R4400 is an upgrade to that. When compared with the 486, the R4400 offers more perfor- mance in the same price range.

—effrey Child

Chorus spreads micro- kernel-based UNIX

Chorus Systemes (Paris, France) appears to be the most agreeable operating system company around. Last year Chorus con- cluded arrangements with IsI Soft- ware Components Group (Santa Clara, CA) to link its microkernel- based UNIx-compatible distributed operating system with ISI’s psOs+ realtime kernel. Recently, Chorus moved to support Sco’s (Santa Cruz, CA) PC-based UNIX.

Now Chorus has entered into an agreement with UNIx System Labs (Summit, NJ), the guardian of UNIX System V Release 4 (SVR4). Its aim is to let Chorus microkernel

technology evolve in step with SVR4, so that large system and re- altime system vendors have an SVR4-compatible microkernel mi- gration path for future develop- ment. Topping this off is an agree- ment with Tandem Computers (Cupertino, CA) to develop micro- kernel-based SVR4 fault-tolerant operating system technology. Ac- cording to Chorus, such technol- ogy will be scalable from embed- ded realtime systems to large mainframe computers.

—Tom Williams

Benchmarks proposed for fuzzy logic

A suite of benchmark programs de- veloped by Togai Infralogic (Irvine, CA) has been proposed as a means of measuring the performance of processors executing fuzzy logic in- ference code. The benchmarks are three fuzzy rule bases at different levels of complexity: simple (with seven rules, each having two input variables and one output vari- able); medium (14 rules of three in- puts and two outputs); and com- plex (25 rules of seven inputs and three outputs).

Togai has released results of tests run on four processors, the Motorola 68HC11, Hitachi H8/300 and -500 and Intel 8051 (which showed the highest performance). There will no doubt be many ques- tions from vendors as to how the code was produced, what inference methods were used and whether code was optimized. When this in- formation is available, vendors may be able to use these bench- marks as a starting point for a common suite that will help de- signers pick price-performance points for fuzzy-based designs.

—Tom Williams

ViaLink helps QuickLogic cut FPGA prices

QuickLogic’s (Santa Clara, CA) ViaLink process technology has been moved from codeveloper VLSI Technology’s (San Jose, CA) pilot line to its high-volume production facility in San Antonio, Tx, produc- ing improved yield and lower wa- fer cost that’s enabled the FPGA vendor to reduce pasic 1 prices by up to 33 percent. “As we move to high-volume production of our

10 DECEMBER 1992 COMPUTER DESIGN

products, we are pleased to be able to pass the cost savings on to our customers,” said David A. Laws, QuickLogic’s president.

vis! Technology recently an- nounced that it will use the Via- Link element as the basis for what it calls programmable Functional System Blocks (pFsBs), cells that provide field-programmable capa- bilities embedded in asic devices. These pFsBs will be used to de- velop embedded memory elements (vROMs or ViaLink ROMs), embed- ded logic elements and custom ViaLink products. Asics built with pFsBs will offer visual and electri- cal security.

Don Ciffone, vice-president and general manager of VLSI’s product divisions, says, “With the ability to include field-programmable struc- tures directly on ASIC and ASSP chips, customers now have unprec- edented flexibility in the design of secure, high-performance systems that can be highly differentiated from those of their competitors.”

—Barbara Tuck

Vitesse prices GaAs ASICs to beat BiCMOS

With 1,500, 7,000 and 13,000 gates, the new 0.6-l1m VIPER GaAs gate arrays from Vitesse Semicon- ductor (Camarillo, CA) are sized for the majority of designs today and offer two to three times the perfor- mance of competing BiCMOS arrays at comparable cost, claims the com- pany. “With the introduction of our VIPER arrays, cost is no longer the issue when comparing GaAs with competing BiCMOS technologies,” says Lou Tomasetta, Vitesse presi- dent and CEO. “Our H-GaAs tech- nology is more mature than most BICMOS processes currently offered. The real issues today are reducing design time through simplified sys- tem architectures and increased performance margin.”

Housed in plastic and aimed at system designs running at 50 MHz and above, the VIPER gate ar- rays deliver shorter gate delays, lower power requirements and better design margins than Bic- mos. According to Vitesse, a two-in- put NOR gate has a typical un-

| loaded delay of 60 ps, while

dissipating only 0.18 mW. “For ap- plications above 75 MHz, there

Continued on page 12

: & IDT's Dm ories Fast Access Sharing one straw has never been the ideal answer, and only IDT’s dual-port memories are the perfect solution when a processor and a peripheral need to share the same data. True sharing means neither side has to wait until the bus is free to access data—they each have individual access to the entire memory array, increasing

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EWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS BRIEFS NEWS

Continued from page 10

are no other Asic technologies that can compete with the price-perfor- mance of VIPER,” boasts Bob Nunn, vice-president and general man- ager of ASIC products at Vitesse. —Barbara Tuck

A kinder, gentler EDIF?

The Electronic Design Interchange Format (EDIF) committee recently unveiled version 2.9.0 of the beleaguered EDIF standard, in hopes that the updated release will rectify the inadequacies of pre- vious versions. For the past four years, the former release, EDIF 2.0.0, has been the primary means of exchanging data among CAD, CAE and test tools, but ambiguities in the standard’s syntax have re- sulted in incompatibility among so- called “epiF-standard” tools. “Release 2.9.0 is the result of years of engineering staff hours and millions of dollars,” says Rich Goldman, engineering manager of the semiconductor vendor program at Synopsys (Mountain View, CA) and chair of the EDIF technical com- mittee. “We’ve gone to great lengths to clarify the EDIF syntax to make life easier for the EDIF reader. This is where the majority of the problems existed in version 2:0:0.” —Mike Donlin

Modeling information comes online

Electronic transfer of component modeling information may yet be- come a reality, thanks to a distrib- ution agreement between start-up ViewPoint Information Systems (Waltham, MA) and Mentor Graphics (Wilsonville, or). The new company’s offering is different from other component information products because its data is ma- chine-readable. Users can extract symbols and attribute information for schematic, simulation and lay- out programs. ViewPoint has also signed deals with Hitachi (Brisbane, CA), Intel (Hillsboro, or) and National Semiconductor (Santa Clara, CA); these agree- ments should give the company component data faster than other vendors who rely on databook in- formation.

The alliances will come as wel-

come news to EDA users, who’ve been demanding vendor-indepen- dent component information sys- tems that can work with EDA soft- ware. Some industry analysts cite this lack of timely component data as a stumbling block to concurrent engineering strategies.

—Mike Donlin

PCI gets expansion connector

The pci (Peripheral Component In- terconnect) definition developed by Intel (Santa Clara, CA) will soon get an expansion connector specifi- cation, according to the pci Special Interest Group Steering Com- mittee. Introduced in June, PCI was defined as a high-performance local bus to supplement existing bus architectures. The definition only provided for an electrical spec- ification, with the belief that pc makers would be soldering such high-performance peripheral chips as graphics and communications directly on a motherboard using the Pcl specification for electrical interconnection.

The proposed connector uses a Micro Channel-style edge-card con- nection providing 32- and 64-bit in- terconnection. The configuration was selected to keep cost down while providing a high-reliability, high-density connection. The ap- proach will let pcI boards be used in BISA, ISA and Micro Channel sys- tems.

PCI’s acceptance will be further enhanced by a Pc! interface chip in- troduced by Intel (Folsom, cA) late last month. Compatible with stan- dard vo buses such as ISA, EISA and MCA, as well as the new PCMCIA standard, PCI will offer com- mercial and industrial users a new high-speed conduit to Pc- based processors.

—Warren Andrews

Standards set for memory interface

While some vendors pursue PCI and others follow PcCMCIA, a group within the IEEE Computer Society is dealing with advances in tech- nology that have made it possible for traditional storage elements such as disk drives to be reduced in size so they can be directly soldered to Pc boards.

The Computer Society’s P1285 is a standards activity meant to de- fine a new IEEE standard interface to handle just such high-latency, non-volatile memory elements. The interface will be used with ei- ther a single memory element or with many coordinated memory el- ements. Issues of concurrency, latency, bandwidth, extensibility, negotiation, and partitioning are among those to be addressed.

—Warren Andrews

486 rivalry continues unabated

Intel (Santa Clara, cA) and Cyrix (Richardson, Tx) are shooting it out on the 486 frontier. In a November announcement, Cyrix unveiled a 50-MHz chip for desk- tops with write-back caching and burst writes (with a separate math coprocessor). Both compa- nies have announced notebook ver- sions of the chip.

The Intel chip’s key features are 3.3-V operation, on-chip integra- tion of a 32-bit memory controller, an ISA bus controller, and the 8- kbyte cache and math coprocessor that are integral to the 486DX. The processor can interface to 5-V peripherals without translation logic. The lower voltage means that a 486SL actually consumes less power than a 5-V 386SL, while providing more than twice the performance.

At the high end is Cyrix’s clock- doubling cx486S2/50. The com- pany’s cx486SLC/e is an enhanced version of its earlier 16-bit chip. There are versions running at 5 V and 3.3 V, although the low-volt- age version requires external translators in dual-voltage de- signs. The cx486SLC/e system management mode lowers power consumption by 25 percent, com- pared to Cyrix’s earlier version. Chips are sampling at 25 and 33 MHz, although 3.3-V operation is only available at 25 MHz.

Intel’s 486 for notebooks, the i486SL, is shipping in a 25-MHz version. A 33-MHz chip is slated for the first quarter of 1993.

—Don Tuite

12 DECEMBER 1992 COMPUTER DESIGN

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CIRCLE NO. 8

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The DSP/PC lowers your

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board count. Increases reliability. Reduces cost. And it’s available right now, today.

Pel EF : = = MA, BOYS. | 7 =a

Still better, its Media~Link® E i ae a architecture bypasses the ISA bus to accelerate interprocessor communications—and speed up | your applications.

Plus, the DSP/PC board comes with integrated software develop- ment tools, including libraries, high-level language support, and source-level debugging.

So discover an entirely new

SbSUAMAMAH{AMALAASSELMAMRELA UCASE

meaning for motherboard. Call

ee

Spectrum Signal Processing today for your DSP/PC Applications Booklet, or for the name of your local distributor.

In the U.S., call 1-800-663-8986; in Canada and worldwide call 604-421-5422. Fax: 604-421-1764.

SPECT rum ee

YS gheatre oe a) K ; , * MCECUORSELERNG SEGREORERGOKON AAEGUGRGNASCEE “eeceucoecinsta Putting DSP to work :

CIRCLE NO. 9

: power of embedd

FORCE COMPUTERS Inc. 3165 Winchester Blvd., Campbell, CA 95008-6557. Prof.-Messerschmitt-Str. |, W-8014 Neubiberg/Manchen. All brands or products are trademarks of their respective holders, © 1992 FORCE COMPUTERS Inc.

CIRCLE NO. 10

This is one of those times when you just have to seize the day. Because opportunities like this are rare indeed. You see, FORCE is the only company licensed by Sun to put SPARC= station . 2 tech-

nology Choose from a range of systems, for a on VME. highly integrated solution.

So we're the only ones who can give you validated hardware and software compatibility. Allowing you to run SunOS” with any of your SPARCstation 2 applications and peri- pherals. Without a hitch.

We also have a whole new family of SPARC 2 products. With everything from

Our CPU-2CE features

a 40MHz SPARC Qur CPU-2CE (6U)

RISC microprocessor, delivering 28.5 MIPS. board to the teraforce

20-slot system. Giving you the perfect combination of real-time and UNIX.

And our SPARC products pro- vide the broadest software offering of any RISC architecture.

So if you want a better grasp of embedded SPARC, call for a free brochure. 800-237-8863, ext. 5. Or in Europe, at 49.89.608-14-0.

Because there's no SPARC reason to let all this power slip through your fingers. "te

SCE

eo

Looking for the kernel that

makes application debugging

both quicker and easier?

jij.

Look to KADAK for the AMX™ real-time multitasking kernel featuring the InSight™ Debug Tool.

AMxXand InSight cooperate with such industry standard source level debuggers as CodeView,” FreeForm}" Turbo Debugger™ and XRAY™ But that’s just the start.

With InSight, a single keystroke will give youa full screen view of all your tasks, timers, mailboxes, messages, semaphores and event flags. Plus, the InSight Profiler will expose those unexpected task

Ww

activities and timing effects.

You'll find AMX with InSight speeds

™ you through the JA\MWIK testing process letting you get

your products to market quicker than ever —one good reason to count on KADAK.

For a free Demo Disk — or to order the AMX and InSight Manual for only $85us — contact us today. Phone: (604) 734-2796

Fax: (604) 734-8114

Count on KADAK.

KADA

KADAK Products Ltd. Setting real-time standards since 1978. 206-1847 West Broadway, Vancouver, BC, Canada, V6] 1Y5

AMxX is a trademark of KADAK Products Ltd. All trademarked names are the property of their respective owners

CIRCLE NO. 11

80386SX / 80386DX / 80486SX / 80486DX INDUSTRIAL SINGLE BOARD COMPUTER

TWO YEAR WARRANTY

All TME products come with Two Serial ports, One Bi-direc- tional Parallel port, Floppy & IDE Hard Disk Interfaces.

TME Toronto MicroElectronics Inc.

Hope a Rd. #1 Mississauga, Ontario, L5T-1C4

HOP486

* 20/25/33/50Mhz, 80486SX/DX

* Up to 48Mbytes on-board memory

* Optional 256K write back cache memory

HOP386C

* 25/33/40Mhz, 80386DX * Up to 32Mbytes on-board memory,

* 128K write back cache memory

HOP386SXC * 16/20/25Mhz 80386SX * Up to 16Mbytes on-board memory

* 64K cache memory * Up to 1.5Mbytes FLASH EPROM on-board

Tel: 416 564-4833 » Fax:416 564-4768

CIRCLE NO. 12

18 DECEMBER 1992 COMPUTER DESIGN

COMPUTER Jechnology

and Design Directions

~ EDITOR-IN-CHIEF/ASSOCIATE PUBLISHER PUBLISHER John C. Miklosz, Ph.D., (508) 392-2114

SENIOR EDITORS Warren Andrews, Computers & Subsystems (508) 283-2102 Barbara Tuck, ASICs & ASIC Design Tools (516) 473-1661 Michael G. Donlin, CAE/CAD Tools (508) 392-2123 Tom Williams, Software & Development Tools (408) 335-5514 Don Tuite, integrated Circuits (415) 365-5656 Jeffrey Child, New Product Developments (508) 392-2126

CONTRIBUTING EDITOR Stephan Ohr, Analog & Mixed-Signal (908) 232-1380

OEM INTEGRATION Senior Editors John Mayer, Technology & Product News (617) 484-5804 Frank Caruthers, Special Reports (215) 993-9595

MANAGING EDITOR: Arlyn S. Powell, Jr.

CHIEF COPY EDITOR: Annette M. Staron-Wilson

COPY EDITOR: Kym Wilson Gilhooly

PRESENTATION MANAGER: Richard Sarno

EDITORIAL ASSISTANT: Claire Ellis

ART DIRECTOR: Jan Horner ILLUSTRATOR: Meg Benner

AD TRAFFIC MANAGER: Kelly Rice, (508) 392-2198

CIRCULATION DIRECTOR:

Robert P. Dromgoole, (918) 832-9213

CIRCULATION MANAGER: Paul Westervelt, (918) 832-9287

PUBLISHER David L. Allen, (508) 392-2111

ASSOCIATE PUBLISHER/ NATIONAL SALES MANAGER: Tim L. Tobeck, (508) 392-2116

nnWell

PUBLISHING COMPANY

Advanced Technology Group Dr. Morris R. Levitt, Senior Vice-President Leslie P. Cypret, Vice-President, Administration One Technology Park Drive P.O. Box 990, Westford, MA 01886 Tel: (508) 692-0700 J Fax: (508) 692-0525

Postmaster: Send change of address form 3579 to COMPUTER DESIGN Circulation Department, Box 3466, Tulsa, OK 74101

ATTENTION RETAILERS: To carry Computer Design in your store, contact International Periodical Distributors at 1-800-999-1170, ext. 447 (dealer calls only)

VBPA ABP

The DK516C-16 Winchester is another legend in a distinguished tradition of Hitachi mass storage products. Hitachi believes that product development starts with the pursuit of maximum reliability. Thats why all of the DK516s key compo- nents are designed, built, and tested in- house by Hitachi.

Legendary Performance

Hitachi backs up this reliability with equally-impressive performance. The DK516C-16s SCSI interface provides a maximum data transfer rate of 5.0 Mbyte/ sec (synchronous), with a 256-Kbyte data buffer and read look-ahead cache. Average seek time is a quick 13.5 ms.

Authorized Distributors CONSAN STORAGE SOLUTIONS 1800. 229-DISC IA, IL, IN, KS, KY, M

MO, ND, NE, OH; PA'(412), SD, WI

EMJ AMERICA INC. 919-460-8861 DC, DE, MD, NC, NJ, SC, TN, VA, WV

S, NC, SC, TN

LAW-CYPRESS DISTRIBUTING co. 1-800-310-6220 AK, CA, HI, OR, V

For ESDI applications, choose the DK516-15. This 1.54-Gbyte drive pro- vides a 14 ms average seek time and a 2.75 Mbyte/sec data transfer rate.

From a Legendary

$62 Billion Company

Both DK516 drives are brought to you by Hitachi, a company renowned for mass storage reliability and innovation. According to a recent independent end- user site survey by Reliability Ratings, Hitachi drives had the highest Field MTBF and the lowest percent failure rate for any OEM drive rated. Fully 100% of the users surveyed would pur- chase the Hitachi drives again.

GENTRY Sree deena ENG. R SQUARED DISTRIBUTING rea opesere ce: AL, DC var ne A, LA,

1-800-777-3478 AZ, CA, CO, ID, MT, NM, NV, OR, UT, WA, WY

SIGNAL COMPUTER PRODUCTS 508-263-6125 CT, MA, ME, NH, NJ, NY, PA, RI, VT

And to back our reliability, we offer one of the longest warranties in the industry. The legend continues. For more information on the DK516, or our new 3.7-Gbyte 5.25" or 1.4-Gbyte 3.5" drives, call 1-800-HITACHI.

Hitachi America, Ltd.

Computer Division

Peripheral Sales & Marketing, MS:500 2000 Sierra Point Parkway

Brisbane, CA 94005-1835

HITACHI

Our Standards Set Standards

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HITACHI CANADIAN 416-826-4100 CANADA

Survey was conducted independently by Reliability Ratings, Needham, MA 02191. The data is from a publicly available report. Reliability Ratings is not affiliated with Hitachi, Ltd., or its subsidiaries,

and does not endorse its products.

Call Hitachi for a free copy of the survey.

CIRCLE NO. 13

Do what most everyone else does.

Control your next embedded system with a micro- processor from Motorola’s 32-bit 68000 family.

Whether your system calls for high performance, low cost, functional integration or a combination of all three,

we've got chips that'll meet your needs.

If cost is your first con- cern, take a look at our industry standard 68ECOO0 micro- processor. It delivers 32-bit performance for $2 and change.

Which makes it perfect for everything from low-end

printers to consumer electronics.

Or if you're in the “speed is everything” camp, consider our 68EC040. A streamlined screamer delivering 29 MIPS of sustained performance, itll run the pants off RISC controllers in high-end appli- cations. At a lower overall system cost.

Or maybe you need

CONTROL CLUDING COsfis.

special functionality. Like built-in multiprotocol com- munications, direct memory access, or sophisticated timers. Our 68300 line of integrated processors comes fine-tuned for a wide variety of applications, from telecom- munications to hand-held computers.

And because they're integrated, they take up very little space.

A quick glance across the page will show you there are many more 32-bit solutions where those came from.

Namely, from Motorola. The company that controls more 32-bit embedded sys-

CIRCLE NO. 15

Motorola and the ® are registered trademarks of Motorola, Inc. © 1992 Motorola, Inc. All rights reserved.

tems than the rest of the world combined.

For a free copy of our 68000 Family Brochure, call 1-800-845-MOTO.

And get everything under control.

(AA) MOTOROLA

BEDITORIAL

“A technical conference in these times has to offer enough...to make your sacrifice in time and money worthwhile. We think we’ve come up with an approach that does that.”

John Miklosz Associate Publisher/ Editor-in-Chief

L

Computer Design takes over A & M-S Design Conference

W ell, the second annual Analog & Mixed-Signal Design Con- ference is behind us and, with so many of us away from the West- ford office on the day of our Halloween party, we again failed to walk away with any prizes. This was the second year in a row that we came up empty-handed and, determined not to let that happen again, we entered into an agreement with Miller Freeman, the original sponsors of the A & M-S Design Conference, to take over full responsibility for future A & M-S conferences. Our first move was to change the scheduled date for next year’s conference from the last week in October to the last week in January, 1994!

But we’re doing more than just changing the date—we’re re- vamping the entire format of the conference. As A & M-S was origi- nally conceived, it was the conventional conference/exhibition, with technical presentations and sessions running during the same hours that the exhibit floor was open. We think we’ve come up with a better way to stage conferences as tightly focused as A & M-S. We’re testing the approach with RISC ’93 in March (see pages 38 and 39) and Fuzzy Logic ’93 in July. The basic idea is to eliminate the traditional exhibits and place the conference at- tendees, as well as the presenters, in a close-up, face-to-face, “total immersion” environment that will expose them to the relevant technologies, tools and applications throughout the entire three days of the conference, morning till night.

With this new format, there’ll be half-day tutorials, one-hour lec- tures, multipaper application-oriented sessions, two-hour after- noon demonstration workshops (providing the opportunity to get some hands-on experience with various design and development tools), and evening rap sessions (with beer and snacks provided). What’s more, we’re throwing lunch into the package on each day of the conference, with each lunch session featuring a distin- guished speaker—a design guru, if you will.

These are tough times for everyone—for designers and design managers at OEMs and system houses, and for vendors of ICs, ASICs and design and development tools. Money is tight and, prob- ably more important, time is tight, with many designers, design managers, product managers, and marketers doing one-and-a-half jobs. A technical conference in these times has to offer enough— and enough value—to make your sacrifice in time and money worthwhile. We think we’ve come up with an approach that does that. What do you think?

22 DECEMBER 1992 COMPUTER DESIGN

The Goal:

Design the world’s only multi- frequency Radar Target Gener- ator System able to simulate hostile threats on the military’s diverse radar systems.

The Problem:

To get the needed horsepower, sixteen 68040 CPU boards were required. However, with this many boards, VMEbus band- width limits would severely degrade system performance making the project unfeasible.

The Solution:

Synergy’s V420 dual 68040 SBC. After evaluating several pro- ducts, KOR Electronics selected eight V420s which could deliver 320 MIPS without VMEbus bandwidth degradation.

“Not only did we meet our project performance goals,

we were able to

reduce our costs by 40%.”

“ Synergy’s dual ‘040 outperformed all other boards I've evaluated in the last five

years,”

—KOR Electronics Garden Grove, CA

Unexpected Benefits: Synergy’s dual ’040 solution cut KOR’s hardware requirements by 50% while vastly increasing system reliability. These un- expected benefits reduced sys- tem costs by 40%.

In Synergy, KOR also found a design partner with strong integration expertise and de- pendable customer support.

“I recommend you call Synergy today.”

Next time you need high performance SBCs, do as KOR Electronics did. Call Synergy Microsystems. You'll be as satisfied as they are.

microsystems

High performance SBCs for demanding applications. SYNERGY MICROSYSTEMS, Inc. 179 Calle Magdalena, Encinitas, CA 92024, 619-753-2191, Fax 619-753-0903

CIRCLE NO. 16

Complete RealTime

Operating System...$995!

Don't be fooled by higher priced realtime systems! RTMX comes complete and ready to run with all standard

BSD utilities, C and C++ Compilers, C source de debugger, editors, and full a

Syn networking with NFS.

1003. | Tool Set*

features include: POSIX realtime xo task scheduler, shared physical

memory, message queues, high resolution

timers, semaphores, software signals and

realtime file support.

RTMX_ systems, with X Windows and Motif, are $1895. Target systems are available starting at $295.

*POSIX 1003.2 and 1003.4 are Draft Standards CIRCLE NO. 17

High performance realtime

For more information:

RTMX-UniFLEX Inc. 800 Eastowne Dr., Ste 111 Chapel Hill, NC 27514

(919) 493-1451 Fax: (919) 490-2903 Email: krl@rtmx-uniflex.com

second Precision er Timing Modules + Event Time Capture

on/ * Multiple Processor Synchronization

penedic Pulses/interrupts

Poe “Call today for our Cor atey Synchronization Products Catalog

- BANCOMM. Division of Datum Inc 6541 Via Del Oro, San Jose, CA 95119 Tel: (408) 578-4161 Fax: (408) 578-4165

STDbus

CIRCLE NO. 18 24 DECEMBER 1992 COMPUTER DESIGN

CALENDAR

December 13 - 16 1992 IEEE IEDM

Hilton Hotel, San Francisco, cA. The 1992

IEEE International Electron Devices Meet-

ing brings together engineering profession- f als from industry, government and aca-

demia. The meeting features 36 sessions on such topics as solid-state technology, integrated circuits and quantum electronics. Also offered are several short courses, plenary sessions and panel discussions. Contact: Melissa Wider- kehr, IEDM, Ste 610, 1545 18th St Nw, Washington, DC 20036, (202) 986-1137, Fax (202) 986-1139. Circle 366

January 3 - 6, 1993

VLSI Design ‘93

Taj Intercontinental Hotel, Bom-

bay, India. The Sixth Inter-

national Conference on VLSI Design, with the theme Chip, Board and Systems Design in the ’90s, brings researchers and designers to the west coast of India. The four-day program consists of paper sessions, posters, tutorials, and industrial CAD exhibits, covering such topics as CAE/CAD systems, logic synthesis, design for testability, circuit sim- ulation, analog devices, and economic issues. Contact: Rochit Rajsuman, Dept. of Computer Engineering & Science, Case Western Reserve University, Cleveland, OH 44106, (216) 368-5510, Fax (216) 368-2801. Circle 367

January 6 - 8 WEST ‘93 oe ‘ r : yb AFCEA&

San Diego Convention Center, San Diego, aly ry CA. The AFCEA and U.S. Naval Institute

Western Conference & Exposition fea- tures a technical program directed to military, govern- ment and industry professionals in the fields of military weapon systems, computers, communications, aero- space, and electronics. The conference focuses on mili- tary- and space-related issues, joint requirements and naval and drug enforcement applications in imaging. Also offered are technical panels, development courses, career transition seminars, and more than 160 exhibits. Contact: Ginny Bracken, J. Spargo & Associates, 4400 Fair Lakes Ct, Fairfax, VA 22033, (800) 336-4583, Fax

(703) 818-9177. Circle 368 February 22 - 25 EDAC-EUROASIC EDAC-93

cniT Conference & Exhibi- FU ROASIC-93

tion Centre, Paris, France.

EDAC, the European Conference on Design Automation, and EUROASIC, the premier European event in ASIC design, will be held jointly this year to provide a forum for a common discussion on ASIC design and design automation. Sponsored by the EDAC Association, the event is expected to draw more than 80 exhibitors, and covers such topics as design techniques and methodologies, high-level design tools, simulation, and testability. Contact: CEP Consultant Ltd, 26-28 Albany St, Edinburgh, EH1 3QH, UK, +44 31 557 2478, Fax +44 31 557 5749. Circle 369

| \

' it

» wa “our Mother—

So VA

ge

«net Re ady Pe, r SOna/ C "e Ly) 0, 7} le ..

Look in almost every office and you'll find a twisted pair _ outlet right on the wall. But look | for an efficient IC solution to _ make your PC design Ethernet-’ ready and it could drive you right up the wall.

Unless you look to AMD. Our new PCnet-ISA—a true one-chip Ethernet controller—gives you the integrated features you need to make your next PC Ethernet-ready. So you get a complete 1O0BASE-T design in less than five square inches of real estate.

PCnet-ISA is going to save you more than just space. Since your total solution will run you less than $25 in volume, PCnet-ISA will shine on the bottom line.

You'll also save design time, because no ad- ditional memory is needed. And you'll deliver higher performance, because data transfers directly to the host memory, instead of through a local buffer.

The software's ready to go too. Driver support is already available for Novell NetWare? Microsoft

AMD's complete PCnet-ISA solution covers less than five square inches.

LAN Manager, Banyan Vines? Artisoft LANtastic? SCO UNIX? and others.

AMD has over 15 years of experience in net- working. PCnet-ISA is yet another in a long line of networking IC solutions from AMD for both Ethernet and FDDI LANs. Our cooperative part- ners include such industry leaders as DEC, HP. and SynOptics. So when you're working with any of AMD's networking solutions, you'll get the engineering support you need just by picking up the phone.

And when you're ready to go to work with PCnet-ISA, call 1-800-222-9323 and ask for Literature Pack 16M. Then plug into a network- ing leader called AMD.

ct

Advanced Micro Devices

901 Thompson Place, P.O. Box 3453, Sunnyvale, CA 94088. © 1992 Advanced Micro Devices, Inc PCnet is a trademark of Advanced Micro Devices, Inc. All brand or product names are trademarks or registered trademarks of their respective holders.

CIRCLE NO. 19

The ADSP-21020: with an enhanced Harvard architecture, you benefit Srom the highest perfor- mance and flexibility available in a floating- point DSP today.

Compared to the ADSP-21020, everything else is sub- standard. It’s got the performance DSP designers want for ultra- demanding applications, like image

processing, graphics, military, voice

1ps/100 MFLOPS

« nition. At 93.3 M and a 1024-point complex FFT

benchmark in 0.58 ms, the ADSP-

21020 is at least twice as fast as

Introducing the With twice the performance and it sinks the competition

anything else on the market. Ask for our “Floating Point Competitive Benchmarks Comparison” and see for yourself.

For even more affordable per-

formance, consider the ADSP-21010.

For just $49.90 (in 100s) you get

a floating-point DSP processor

Which is code-compatible with our

new family of floating-point DSPs

offering high performance and

a path to higher on-chip integration.

Just as with the ADSP-2100 family

of fixed-point DSPs, these products

use an enhanced Harvard archi-

ADSP-21020 Performance Benchmarks ¢ 1024-point complex FFT (radix-4 with digit reverse ): 0.58 ms ¢ 1024-point real FFT (radix-2): 0.34 ms e Divide: 180 ns el/Vx :270ns ¢ Cubic Bezier evaluation: 300 ns

¢ Cubic B-Spline evaluation: 450 ns

tecture for optimum performance

and exibility

too. With development tools that are easy to use and accelerate your

code-writing and time-to-market.

Authorized North American Distributors: Alliance Electronics 505-292-3360 + Allied Electronics 800-433-5700 * Bell Industries 310-826-2355 + Future Electronics 514-694-7710 (Canada) 508-779-3000 (USA) * Hall-Mark Electronics 214-343-5000 * Newark Electronics 800-367-3573 * PioneerStandard Electronics 800-874-6633 * Pioneer Technologies Group 800-227-1693 * WYLE Laboratories 800-866-9953 * Zentronics 416-507-2600 (Canada)

ADSP-21020. a complete tool kit for $995.00, in floating-point DSP

The EZ-KIT enables you to evaluate a proto- type design quickly,

with modules to pro- we ecm 4 ae

2 | gram and simulate both the . e——— Analog Devices’ EZ-KIT: the most extensive (and least expensive) DSP development tool kit on the market today, with software development tools, a powerful simulator, the EZ-LAB board for prototyping, and (in the EZ-KIT-PLUS), a C Compiler and source-level debugger.

ADSP-21010 and ADSP-21020; link

in optimized library routines for key available for just $1,995. You can do EZ-KIT-PLUS are only valid through

DSP algorithms; and run the applica- real-time in-circuit emulation with March 31, 1993. To order your EZ-KIT

tion on the EZ-LAB Evaluation Board EZ-ICE, and soon you'll be able to or receive a product information that’s included. At $995, it’s a very run Ada coc packet, ca]

lus at (617) 461-377]:

2 1)20/21010 as well.

, : »NACK: % athe a ace.an cost-effective tools package. For System on the 4 you can even place al all of the above, plus C Compiler, Now is the time to get on board order with your credit card. runtime library, and source-level with floating-point DSP. Because

ANALOG debugger, our EZ-KIT-PLUS is these great prices on our EZ-KIT and DEVICES

Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106. Distribution, offices and application support available worldwide. EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc, SPOX is a registered trademark of Spectron Microsystems Corporation

CIRCLE NO. 20

eK

— the heart your system and the key to error-free interboard data transfer.

vA

BUSTRONIC’s high-performance backplanes are designed to meet and exceed today’s high-speed computing requirements. With incremented CPU N

and logic speed, there is a greater concern for low noise and improved reliability. ‘ BUSTRONIC has developed the best possible products available for today and the foreseeable future. Each signal line is matched and balanced for the optimum in char- \t acteristic impedance. All backplanes offer versatile power distribution and a connection \¥ scheme with distributed decoupling capacitors for both high and low frequency.

Discuss your custom or MIiL-spec requirements with our engineers.

b Please contact us for more information.

Bustronic Corp. * 44350 Grimmer Blvd. * Fremont, CA 94538

ed ee f all TEL (510) 490-7388 * FAX (510) 490-1853 CIRCLE NO. 21

BTECHNOLOGY VIEWPOINT

Tom Clark on: FPGA design

arrays (FPGAs) and complex programmable logic

devices (CPLDs) have two basic choices when it comes to design methodology—structural and be- havioral. Until recently, the preferred choice among most designers was structural design—namely, sche- matic capture. But a strong movement is underway toward a shift in design methodology.

Today, many systems designers are moving away from schematic design entry and are taking advan- tage of the higher level of abstraction offered by behavioral design methodologies. This doesn’t mean that engineers are phasing out their schematic cap- ture products. Rather, it signifies a shift toward a new design environment that utilizes hardware descrip- tion languages (HDLs) as its core, and alters the role of schematic capture to provide less design and more documentation.

i ogic designers using field programmable gate

Bf New architectures push change

Pushing this shift in methodology into the spotlight is the immense popularity of FPGAs and CPLDs. These new device architectures combine the best features of ASICs with the best characteristics of PLDs. Initially, schematics were the entry vehicle of choice, primarily because many of the early adopters of FPGAs were ASIC designers. Schematic entry is also inherently a lower- level (and so more detailed) representation of a design than a behavioral description, and offers better con- trol over the silicon.

In addition, FPGA vendors have realized that design at the schematic level effectively locks a designer into one supplier’s technology. Anyone who’s changed a gate-array vendor in midstream immediately knows why—to retarget a schematic-based design to another vendor, you have to redo much of your work. With FPGAs, the situation is even more severe. Whatever one-to-one remapping you might get away with in gate-array retargeting is impossible, or at least hope- lessly inefficient, for moving between FPGAs. This is

Thomas R. Clark, president and CEO, Data I/O Corporation,

Redmond, WA

because each FPGA vendor’s architecture and granu- larity are dramatically different.

Bf The move to behavioral methods

Several trends are weaning FPGA and CPLD users from schematic capture, and shifting them to behavioral methods. The first is the increase in the number of device vendors; the second is the increase in device density; and the third is the advent of new behavioral methodologies capable of handling the complexity offered by FPGAs.

When FPpGas were first made available, there was only a single vendor of choice—Xilinx. Later, Actel, AT&T and Texas Instruments entered the market. With these limited choices, designers weren’t averse to a vendor-specific toolset. Today, however, a growing number of silicon vendors have FpGa offerings. Add to this the growing number of complex PLD solutions, many of which offer comparable density and higher performance than their FPGA counterparts, and it’s obvious you have many choices.

In June’s Computer Design Technology Viewpoint, Cyrus Tsui provided an excellent profile of our indus- try, and we agree with him that there’s little chance of an industry architectural standard in the near future. As a result—and to combat the hype and false promises accompanying some device introductions— many designers have adopted one or two “pet” archi- tectures. This benefits the few vendors who were first to market with FrpGas, and is a serious obstacle to those who’ve come later.

The problem with this defensive strategy is that all

COMPUTER DESIGN DECEMBER 1992 31

ETECHNOLOGY VIEWPOINT

FPGAs aren’t created equal. In fact, there are signifi- cant differences in how well particular applications map to various architectures. Some FPGAs are signif- icantly better at certain kinds of circuits than at others, and even in a particular circuit class (datapaths or state machines, for example), there are typically only one or two architectures that best match a given, specific circuit. Narrowing down the number of candidate architectures may be a perfectly rational way to deal with the complexity and economic rigor of a market featuring so many choices, but it’s not the best way to match silicon to a design and ensure high utilization and top performance.

This abundance of choice is a leading factor in the shift to behavioral entry. The higher the level of abstraction designers work at, the less they’re tied to any particular piece or class of silicon, and the more readily the design can be retargeted. Behavioral entry lets you migrate designs between different architec- tures, letting you choose the one that best fits your application.

Perhaps the most important factor leading to a methodology shift is the fact that FPGAs and CPLDs are already meeting the density requirements of the ma- jority of today’s gate-array designs. At this level (around 10,000 gates), design by schematic is still practical, but efficiency is questionable. The higher level of abstraction offered by behavioral design methodologies becomes a major factor in overall de- sign efficiency. The use of HDLs for design entry lets you describe a design in a device-independent and higher-level fashion, with synthesis routines complet- ing the tedious and time-consuming work of matching appropriate design elements into correct architec- tural features.

The third force in the shift from schematic to be- havioral entry is the development of logic synthesis for FPGAs. FPGAS present a more difficult technological challenge for synthesis than the less constrained ASIC. The architectural variations among different vendors’ FPGAS are vast in comparison to those evident in gate arrays.

El Device fitters to the fore

It’s only in the last two years that synthesis has become sufficiently practical to work its way into the mainstream, but it now offers a viable solution for rpacas. At the forefront of this synthesis movement are software algorithms called device fitters. Device fit- ters, in the same vein as the FPGAs they support, have borrowed techniques and algorithms from traditional Asic design software, and have melded them with generic PLD optimization routines and derivatives. A device fitter is a program that synthesizes a generic logic description into an implementation that is optimal for a particular architecture. It works ina fully automatic mode, but also lets you manually specify placement, routing criticalities, buffering, and other characteristics. The fitter, rather than the de- signer, takes on the burden of knowing the low-level details of the target silicon intimately enough to efficiently implement an application into a circuit. Today’s device fitter synthesis capabilities dispel many previously held beliefs that prevented FPGA behavioral methodology from being widely adopted. Many assume, for example, that the best way to run

32 DECEMBER 1992 COMPUTER DESIGN

synthesis is on a complete design. This is not true— synthesis performs far better if run on a design’s submodules. Many also believe that synthesis will always improve a circuit’s size or speed. Again, this isn’t true. There are classes of circuits upon which synthesis nearly always fails, and upon which it should never be run. Many think that schematics are as good a candidate for synthesis as behavioral de- signs. This also isn’t true—schematics contain valu- able knowledge about how a circuit should best be structured, knowledge that’s often beyond a synthesis algorithm’s ability to divine.

The ideal design solution includes the ability to use behavioral entry as well as schematics, applying each to the portions of the design for which it’s best suited. Making these points clear to the design community— educating users through design examples and train- ing—is a prerequisite for achieving full acceptance of behavioral entry in the mainstream.

B Applying benchmarks

Data 1/0, as well as other vendors, have been involved in the past year in the PREP benchmarking effort. This Programmable Electronic Performance consortium is a group of PLD manufacturers and tool vendors whose objective is to develop a suite of benchmarks to accu- rately measure the functional capacity and speed performance of either PLDs or FPGAS. PREP was not formed to standardize such items as physical inter- faces, pinouts, architectures, or deal with spec sheet issues, such as electrical characteristics. The PREP solution is an important and useful first step toward helping designers understand how the FPGA architec- ture announcements they see in the press every month translate into gains in their ability to design and deliver the products their markets demand.

Ultimately, we believe benchmarking will move to the desktop, where you can decide for yourself which devices give the best gate utilization, the best in-sys- tem speed, the best economic choice. That’s why we’ve spent considerable energy in the past two years de- veloping and constantly improving and adding to our list of device fitters. Our goal is to see designers armed with a universal front end that allows device-indepen- dent design, along with a rich back end, powered by device fitters, that can intelligently retarget designs between the full spectrum of architectures—and that lets you benchmark your circuits in any candidate device.

Movement in the CAE market, however, is slower than we’ve hoped for. Behavioral entry is important and its momentum is building, but it will not totally replace schematics. Automatic device fitting has ap- peared, but designers will always want additional control. As we’ve learned elsewhere, the best revolu- tions are those that augment and build upon the past.

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43 TEXAS INSTRUMENTS

00-7536

ETECHNOLOGY DIRECTIONS

INTEGRATED CIRCUITS

New clock chips are analgesic

Don Tuite, Senior Editor ynchronizing the edges of a Ss distributed clock so that every chip in a system is clocked at the same instant has been made eas- ier with new chips from Vitesse (Ca- marillo, CA), TriQuint (Santa Clara, CA) and Cypress Semiconductor (San Jose, CA). All the chips give you flex- ibility in routing clock lines on a cir- cuit board. In some cases, prototype timings can be trimmed ad hoc using the programming inputs to the chips. Some of these clock distribution chips also offer frequency multipli- cation and division. Division lets you reduce the frequency of a clock that is being sent off the board, reducing potential EMI problems; multiplica- tion lets you increase it again. Be-

for run-length headaches

cause these chips use phase-locked loops (PLLs) that feed selected inputs back into the loop, they can be oper- ated as zero-propagation-delay clock | distribution chips. Propagation de- lays are 1 ns or less.

Bl cypress breaks rules

Despite the similarities between the purposes of these chips, there are | differences among them—most no- tably, between the gallium-arsenide (GaAs) devices from Vitesse and

SEO ERT

| while providing a larger array of timing options than bilevel inputs.

It’s easier to understand the

_ differences between the chips by

thinking of them in terms of the voltage-controlled oscillator (Vvco). In all these devices, the vco runs at a multiple, N, of the clock frequency. The higher the vco frequency, the better, in terms of the precision with which you can control the outputs. In the GaAs parts, the oscillator

_ runs at a speed as high as 840 MHz.

_ TriQuint and the silicon device from |

Cypress. Not only did Cypress vio- late the “rule” that says you can’t run a silicon PLL that fast, but the com- pany’s engineers designed trilevel | inputs that simplify programming

FEEDBACK CLOCK IN

SKEW CONTROL 0 —

SKEW CONTROL 1

The basics of skew control

SKEW CONTROL N eee

OUTN

tials.

—

Clock distribution chips that let you control the relative skew of their various outputs consist of two parts. The first part (green) is a phase-locked loop that samples one of the outputs via an external link. This locks the output to the input, providing essentially zero propagation delay. It also supplies skew-shifting refer- ence signals, either from running the pit’s voltage-controlled oscillator at a multiple of the input frequency or from tapping selected stages of a ring oscillator running at the clock frequency. The second part (purple) is a skew-control block that uses the signals from the first part to generate outputs that are multiples or submul- tiples of the source clock, or that are shifted in time by controlled phase differen- |

34 DECEMBER 1992 COMPUTER DESIGN

It would be difficult for a silicon part to run that fast, but Cypress uses a trick to produce a precision equiva- lent to running a straight oscillator at 1,300 MHz.

You control the outputs of all these chips in two ways: by programming skew-control input pins, or by select- ing which output is fed back to the input of the PLL. In these ways you are selecting values for N, and for edge placement in various channels.

Bf Flexible output clocks

TriQuint’s 80-MHz GA1000 has six outputs that can be programmed to run at one or two times the input frequency. This means the output frequency can be as high as 160 MHz. There are two skew-control inputs. With all the outputs in phase, the maximum skew between any two of them is guaranteed to be 500 ps. Typical values are 250 ps. In programming the chip, you se- lect a value for N between 4 and 22. You also determine where the rising and falling edges of the output fall with respect to the rising and falling edges of the internal vco clock. Be- cause the vco frequency must be between 320 and 440 MHz, your sys- tem clock frequency determines what values of N are possible, and so what degree of timing precision you can achieve. For example, at 66 MHz, N must be 5 or 6—that is, 330

_ and 396 MHz are the only values of

N multiplied by 66 MHz that fall in the allowable range. Depending on

| which value of N you choose, you can

delay edges in multiples of 2.53 or 3.03 ns. At an input frequency of 55

| MHz and a value of 8 for N, you get

the smallest increment of edge placement, at 2.27 ns.

TriQuint’s 50-MHz GA1110E has six outputs that you can shift in increments of 2.5 ns. The guaran- teed maximum input skew is 500 ps, with the typical being 250 ps. All six

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and Provection CIRCLE NO. 24

anidard for r Data Ree

ssnnevte UTIL Stan

ETECHNOLOGY DIRECTIONS

INTEGRATED CIRCUITS

Output fed back

Output phase shift

QO, Q1, Q4

Q2

Q3

Q5

QO, Q2, Q3

Q1

Q4

0 a ie t

The combination of two bilevel inputs and one of six outputs fed back to the phase- locked loop produces an array of positive and negative skews and inversions.

outputs of the GA1110E operate at the clock fundamental, but you can use the part with TriQuint’s GA1086 or GA1086E 10-output clock buffers, which have nine outputs at the clock frequency and one at half the clock frequency. Both the 1086 chips have very tight output-to-output skew variation—250 ps maximum, and 125 ps typical. The GA1086 specifies a propagation delay of 500 ps and the E-version specifies twice that.

Vitesse’s 70-MHz VSL4485 and VSL4586 each have eight outputs. On two of the 4485’s pins—or on six of the 4586’s—you can multiply the input clock frequency by 2 or 4, or you can leave it at the fundamental. As with the TriQuint chip, combin- ing two skew-control inputs with a choice of which output is fed back to the PLL gives a range of phase shifts at the various outputs. The actual value of the phase shift, relative to the output clock frequency, is deter- mined by three other inputs that Vitesse calls divide inputs.

Like the TriQuint clock chips, the Vitesse chips guarantee 500 ps max- imum skew between outputs. Typi- cal values aren’t currently specified.

Because the Vitesse vco operates at |

frequencies of up to 840 MHz, these chips provide more precise skew con- trol than the TriQuint parts. The smallest possible increment is 1.25 ns.

E Lots of control

Superficially, Cypress’s 80-MHz CY7B991 (TTL Vo) and CY7B992 (CMOS VO) resemble the TriQuint and Vitesse parts. There are several in- teresting differences, however. For one thing, the eight outputs of the two chips are arranged in pairs, and Cypress guarantees skew between members of the same pair to be 250 ps, while claiming that typical val- ues are half that. For another, each pair of outputs has its own pair of skew-control pins, which may be pulled high or low or left uncon- nected. (An internal voltage divider prevents static buildup.)

There’s an advantage to having a larger number of control pins. For each output pair, if the input pins are open, the output is in phase with the clock. Using other input values, you can trim the first two output pairs in increments of one, two, three, or four timing units, and you can trim the second two output pairs in increments of two, four and six

36 DECEMBER 1992 COMPUTER DESIGN

| which you will obtain your tap. In the

| skew control, is determined by the

timing units. The third pair can also be set for one-half or one-quarter of the applied clock frequency, and the fourth pair can be set to one-half the applied frequency or to the inverse of the applied clock.

Because of this simple control method, you can design a board us- ing 991/2 chips to distribute clocks without paying a great deal of atten- tion to trace lengths. Then you can use DIP switches on the skew-control inputs of the chips to trim edge ar- rival times on your prototype board while you observe edge placement on a scope. On production boards, you simply replace the switches

| with jumpers.

Lacking the raw speed capabilities of GaAs, Cypress implemented the VCO in its PLL as a ring oscillator. This device uses a cascade of gain stages

| to achieve the 180° of feedback an oscillator needs in order to work.

Each stage introduces a constant in- crement of phase delay, and the sig- nal tapped off any stage is delayed or advanced relative to a reference by an incremental amount. Instead of selecting a value, N, by which the vco frequency will be divided, you select a number of delay stages, after

Cypress parts the values are 16, 26 or 44. The precision, or degree of

clock period divided by the number of stages. The smallest increment of stage delay is 700 ps.

TriQuint and Vitesse unequivo- cally specify their output rise times: 1.5 ns (max) for 0.8 to 2 V. (For the 10-output clock distribution chips, it’s 1.4 ns.) According to the manu-

| facturers, these values are essential

for Intel’s Pentium P5 or 586 proc- essor. Cypress’s spec sheet cites a rather lackluster 3 ns for the TTL 1/0 part and 5 ns for the CMOs Vo part. According to the company, however, the parts actually slew at about 1

ns/V. Bi For more information about the technol-

ogies, products or companies mentioned in

this article, call or circle the appropriate number on the Reader Inquiry Card.

Cypress Semiconductor

(408) 943-2902 .. Circle 201 TriQuint Semiconductor

(408) 982-0900 .. ares .... Circle 202 Vitesse Semiconductor

(805) 388-7455 . Saat _.. Circle 203

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MARCH 16-18, 1993

9S

HYATT REGENCY SAN FRANCISCO AIRPORT BURLINGAME, CALIFORNIA

WHAT IS RISC ‘93: asc 93 is the premier annual gathering of hardware designers and software devel- opers involved with RISC system architectures; RISC processors, ASIC cores and peripheral ICs; RISC programming and debugging; and the design of RISC-based systems for general-purpose computing, embedded and realtime applications.

THE ATTENDEES: asc 93 is a downto-earth conference aimed at both hardware and software engi- neers and engineering managers responsible for the design and development of products based on RISC processors. Specifically, RISC ‘93 is targeted at individuals with a solid background in electronic/computer system design and develop- ment (both hardware and software), as well as applications programming, who are looking for the most up-to-date infor- mation on the design of RISC-based computers, the design of embedded and realtime RISC systems, programming RISC- based systems, designing ASICs with RISC cores, and specifying and integrating RISC development tools into the overall product development environment.

THE FORMAT: TOTAL IMMERSION

RISC ‘93 has been designed as an intensive 3-day program that will place all participants in a total immersion environment where they'll have the oppor- tunity to attend:

Half-day tutorials that will help clarify the intricacies of the major RISC processor architectures.

A variety of one-hour lectures that focus on specific aspects of RISC architectures, RISC-based hardware design, programming techniques, compilers, and development tools.

Multipaper, application-focused sessions consisting of 20-minute presen- tations by system designers and software developers who've already implemented RISC designs in applications ranging from workstations, graphics, image processing, communications, signal processing and embedded control.

A luncheon on each day of the conference that will be highlighted by an address from a recognized authority on RISC architecture or RISC- based designs.

Demonstration workshops where attendees will be able to get hands- on exposure and detailed information about the latest RISC processors, compilers and development tools offered by leading hardware and soft- ware vendors.

Free-wheeling “rap” sessions, led by RISC experts, on the first two evenings of the conference. Conference participants will have the chance to explore and exchange ideas about any aspect of RISC and RISC-based system design in an informal atmosphere of shirt sleeves, beer and pizza.

MORNING

LUNCHEON/SPEAKERS

AFTERNOON

DEMONSTRATION WORKSHOPS

RAP SESSIONS

LED BY RISC EXPERTS

RISC ‘93 Conference is sponsored by COMPUTER DESIGN # One Technology Park Drive, Westford, MA 01886 TEL: 508-392-2124 ® 800-223-4259 = FAX: 508-692-7780 = Contact: Patti Kenney, RISC ‘93 Conference Coordinator

PARTICIPATION: Suppliers of RISC proces-

sors, ASICs, peripheral ICs and memory, compilers, and development tools, as well as system designers and pro- grammers working on RISC-based designs and applications, are invited to participate in RISC ‘93 by presenting tutorials, lectures, 20-minute application-focused papers or leading one of several evening “rap” sessions. A variety of topics that would be of interest to attendees is suggested in the Call for Papers for RISC ‘93. All presenters receive free admis- sion of all tutorials, lectures, applications sessions, lun- cheons, rap sessions and a copy of the proceedings.

Suppliers of RISC hardware/software or development tools may also participate in RISC ‘93 by sponsoring a demonstra- tion workshop. These workshops will be two hours in length and will be the last formal sessions of the day. They're intended to provide attendees with an intimate, hands-on exposure to a supplier's product or service. The cost of sponsoring these sessions is $1500 for one two-hour workshop, $2700 for two workshops on successive days and $3500 for a workshop on each of the three days of the conference. One complimentary admission to RISC ‘93 for each workshop sponsored is included in the fee.

COMPUTER Technology

1993 INTERNATIONAL TECHNICAL CONFERENCE SERIES

RISC ‘93 is open to all system designers and software devel- opers and the tuition fee covers admission to any tutorial, lecture, application session, demonstration workshop, evening rap session, and the three conference luncheons.

TUITION: $495. Early Bird— Register by Dec.3, 1992 $595. If registered between Dec 4, 1992 - Jan 21, 1993 $695. After Jan 22, 1993 (Tuition includes lunch on all three days

as well as snacks and refreshments during the rap sessions.)

Company group discounts available.

HOTEL ROOMS:

The single room rate at the Hyatt Regency is $108. Call the hotel directly at 415- 347-1234

Be sure to tell them that you are attending RISC ‘93.

YES, 'M INTERESTED ! PLEASE SEND MORE INFORMATION q L] 1 AM A VENDOR Id like to present a: MAIL OR FAX TO: Tutorial (_] One-hour lecture (_] Application session Patti Kenney _] | would like to lead a rap session RISC ‘93 Conference Coordinator i= . ; : COMPUTER DESIGN __| My company would like to discuss sponsoring a workshop — One Technology Park Drive Please contact P.O. Box 990 Westford, MA 01886 CJ] 1 AM A POTENTIAL ATTENDEE: FAX: 508-692-7780 _| I'm interested in attending, send me more details TEL: 508-392-2124 _| I'd also like to lead a rap session 800-223-4259 |_| 1am particularly interested in sessions on NAME TITLE COMPANY ADDRESS M/S CITY STATE ZIP PHONE FAX

CIRCLE NO. 25

ETECHNOLOGY DIRECTIONS

INTEGRATED CIRCUITS

IEDM gets relevant

Stephan Ohr, Contributing Editor

his year, the IEEE conference organizers of the annual Inter-

national Electron Devices Meeting (IEDM), held this month in San Francisco, have added a new theme. They’re asking authors to re- spond to current economic condi- tions, and to assess what the costs of volume manufacturing might look like for the dramatic devices and processes they discuss. Coming from well-endowed and protected re- search laboratories, however, many of the best papers may still have a decidedly pie-in-the-sky feel to them.

One of the most attention-getting papers, for example, is a Matsushita presentation exploring how laser lithography might be used to pro duce 256-Mbit DRAMs, de- vices that even the au- thors acknowledge won't appear until 1997 or 1998. (At previous IEDMs, we should note, the electron- ics industry heard the first discussions and saw the first chip photos of 4-Mbit, and, later 16-Mbit DRAM architectures. )

Two current papers from NEC’s Microelectron- ics Research Laboratories (Kanagawa, Japan), in fact, describe a capacitor structure that the au- thors, Hamada and Watanabe, suggest may be useful for 256-Mbit DRAMs. “This chip will be so ad- vanced,” says the promo- tional material for the con- ference, “it will be able to store 16 photograph-qual-

rays, the authors believe, may be prohibitively expensive. An 1BM/To- shiba/Siemens consortium, for ex- ample, has already committed to X- ray lithography to manufacture 64-Mbit DRAMs with 0.35-um fea- tures, with the companies’ invest- ment expected to exceed $600 mil- lion by 1995. The investment in 0.25-um, 256-Mbit DRAM manufac- turing, is expected to exceed $1 bil- lion by 1999. The Matsushita re- searchers feel that excimer laser operating in the frequency range of visible light are a much cheaper ap- proach.

The excimer laser tested by Matsushita relies on krypton-fluorine and argon-fluorine, as well as a high-

Researchers at Matsushita Industrial Electric Company have

used excimer laser lithography to produce 0.25-\.m isolation pat- terns, the geometry required for 256-Mbit DRAMs. As is the case with many IEDM presentations, it remains unclear whether the Matsushita researchers have hit upon a practical manufacturing method or a laboratory curiosity.

photoresist layer? Or should the photoresist layer be scored directly by the swath of the laser beam? If the latter is the case, then it will take many minutes to score each chip. The process may be cheap, but it will be very time-consuming, and the ex- cimer laser process may turn out to be as practical for high-volume man- ufacturing as E-beam writing proved to be.

Bf Frank discussion needed

Of the 143 IEDM papers from com- mercial companies, IBM had the most accepted (15), followed by AT&T, Mo- torola and Japan’s NEC (10 each). Universities contributed 72 papers, while eight came from government agencies. But it remains to be seen whether these papers offer practical manufacturing tips. “IEDM is traditionally seen as a showcase for new technolo- gies leading to products that will hit the market three to five years down the road,” says Hans Stork, manager of exploratory technology at IBM’s T. J. Watson Research Center (Yorktown Heights, Ny), “but IEDM 1992 will also feature some frank discus- sion about the direction of the industry and the re- search work driving it for- ward.”

An evening panel dis- cussion led by Lew Terman of IBM, for example, will ex- amine the impact of slow growth and increased costs

ity images, or an entire en- cyclopedia of text.”

The chip will have a feature size of 0.25 um, say researchers Endo, Hashimoto and Yamashita, all of Matsushita Industrial Electric Company (Osaka, Japan), in their abstract. Current semiconductor manufacturing relies on photolitho- graphy, but as the feature size of the devices decreases, the dimensions of the photomask—and even the wave- length of the light used to expose the photoresist—must also decrease.

The use of electron beams or X-

resolution stepping method, chemi- cally amplified positive photoresists and a carefully controlled depth of focus for the laser. While the re- searchers have successfully pro- duced 0.25-um and even 0.20-t1m di- mensions using this process, it’s unclear how difficult it will be to adapt the process to high-volume memory manufacturing. For exam- ple, should the laser light be pro- jected through a photomask that mass produces the trenching in the

40 DECEMBER 1992 COMPUTER DESIGN

on technology research. Does it pay to be a leading- edge manufacturer? Or does it make more sense to focus on application- specific products with immediate sales potential?

This is a serious issue for the com- puter giant. William Bowles, direc- tor of IBM’s OEM products marketing group and keynote speaker at Com-

| puter Design’s SysComp forum last

February, used a Silicon Valley analog conference last month to an- nounce the company’s entrance into the market for mixed-signal Asics.

Graphic memory that your imagination run wild.

Memory Part Access Packaging Configuration Features Number Time (ns) Options Availability

Triple Port DRAMs

250K x 4 Fast Page Mode/Block Write MT43C4257/8 80,100 SOJ Now

128K x 8 __ Fast Page Mode/Block Write MT43C8128/9 80,100 PLCC Now

Dual Port DRAMs (VRAMs)

250K x 4 Fast Page Mode/Block Write MT4204256* 70,80,100 ZIP, SOJ Now

128K x 8 Fast Page Mode/Block Write MT42C8128* 70,80,100 SOJ Now

256K x 8 Extended Data Out/Block MT42C8256 70,80 SOJ, TSOP Now Write/Programmable Split

256K x 8 Fast Page Mode/Block Write MT42C€8255 70,80 SOJ, TSOP Now

256K x 8 Fast Page Mode/Block Write/ MT42C8254 70,80 SOJ, TSOP Now Dual Write Enable u

Specialty DRAMs

250K x 16 Fast Page Mode MT4C16256/7/8/9* 70,80 ZIP, SOJ, TSOP 4Q92

‘Low power versions also available

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FON

SEMICONDUCTOR, INC.

2805 E. Columbia Rd., Boise, ID 83706 (208) 368-3900

Customer Comment Lines: U.S. 800-932-4992; Intl: 01-208-368-3410

©1992. Micron Semiconductor, Inc

CIRCLE NO. 26

Te echolo® ey that wor”

y you:

) 4

&

ETECHNOLOGY DIRECTIONS

INTEGRATED CIRCUITS

LDMOS device cross-section

TiSi,

P BODY

N+ BURIED LAYER

P BURIED LAYER

P BURIED

P SUBSTRATE LAYER

Motorola, in one of the most practical papers at IEDM, presents a way to integrate /at- eral double-diffused MOS on a BiCMOS substrate with 0.5-\um devices and maximum frequency (fts) on the order of 26 GHz. These smart power structures will contribute toward the portable RF transmitters of the near future.

of these announcements, Lew Ter- man’s panel may be more dramatic than a polite conversation among

The same week, the company told financial analysts it will close semi- conductor manufacturing plants

“The concern about profitable manufacturing is also evident in a number of papers that describe cost- effective ways to produce new cir- cuits,” insists IBM’s Stork, who heads the publicity effort for IEDM 1992. He cites as evidence an invited paper by Dr. Yoshio Nishi of Hewlett-Pack- ard (Palo Alto, CA), a man who ear- lier led Toshiba’s 1-Mbit DRAM devel- opment effort. The paper questions the conventional view that memory circuits are the best proving ground

| for advanced fabrication techniques

for microprocessors and other dig- ital circuits.

If anything, Nishi’s paper, “ULSI technology toward the next century: driven by DRAMs or MPCs?,” forecasts a split between the processes used to manufacture ultra-large-scale in- tegrated (ULSI) circuits. One process will be used for memory, the other for RISC microprocessors. These chips require two fundamentally dif-

and lay off 40,000 workers. In light | wealthy gentlemen. ferent technology drivers, says Dr.

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Nishi. Where memories require so- | plastics) isn’t an oxymoron, and sug- | neurons in the human brain. Pre- phistication in front-end fabrication, | gesting applications for such materi- | sented by K. Kotani of Tohoku Uni-

RISC microprocessors require expert- | als. | versity (Tokyo, Japan), “Neuron-Mos ise in back-end packaging tech- | A Tuesday, December 15th lunch- | binary-logic circuits” describes ICs niques. It may be too costly to at- | eon session will feature a talk on | that embody real-world “fuzziness” tempt both, Nishi warns. virtual reality by Jaron Lanier, chief | by representing transistor inputs as

’ ; scientist and founder of vPpL Re- | weighted sums of multiple inputs. i Thought-provoking sessions search (Foster City, ca). Also, check | The authors claim that these fuzzy-

The plenary session on Monday, | out a Tuesday evening panel session | logic 1cs reduce the number of tran- December 14th, of which Dr. Nishi’s | entitled “the electronics industry | sistors required to implement ma- presentation is a part, may be the | andthe new world order: technology, | chine vision, pattern learning, most thought-provoking event for | Politics and Industrial Competi- | fault-tolerance, and other ambigu- the general engineering community. | tion.” Organized by the Berkeley | ous decision-making systems.

“semiconductor devices save the | Roundtable on the International There are several sessions, how- earth,” by Yukinori Kuwano of | Economy (BRIE), the panel will dis- | ever, that are bound to have more Sanyo Electric (Tokyo, Japan), ex- | cuss the impact of international pol- | immediate practical impact. The plores the possibilities of increasing | itics (for example, military conver- | two one-day short courses, always energy and reducing pollution | sion) and economic competition on | popular with IEDM attendees accord- through the proliferation of semicon- | the semiconductor industry. ing to the IEEE, will be held on Sun- ductor-based solar cells. In the same In spite of its focus on relevance, | day, December 13th. One course, session, Alan Heeger of the Institute | IEDM will still feature its share of | “Interconnect for the ’90s,” focuses for Polymers and Organic Solids of | gee-whiz ideas that may indeed rep- | on interconnection issues for on- the University of California (Berke- | resent breakthroughs, if somebody | chip, off-chip, module, and PcB sys- ley, CA) will give a presentation dem- | can just figure out what to do with | tems. Interconnections are seen as onstrating that “conducting poly- | them. One of these gee-whizzes is a | the weak link when it comes to in- mers” (or electrically-conductive | paper on transistors that emulate | creasing performance. Presented by

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BTECHNOLOGY DIRECTIONS

Brian Bakoglu of IBM, Bob | Havemann of Texas Instruments (Dallas, Tx) and Arjun Saxena of Rensselaer Polytechnic Institute | (Troy, NY), the course examines the impacts of material, thermal effects and transmission-line behavior on | packaging choices. The other short

INTEGRATED CIRCUITS

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CIRCLE NO. 32

44 DECEMBER 1992 COMPUTER DESIGN

anisms of MOSFETs, including corro- sion, electromigration and stress voiding effects.

“Transistor-level reliability” will be discussed by Akira Toriumi of Toshiba (Tokyo, Japan); “Reliability in multi-level interconnects” will be presented by Ronald Schutz of Se- matech (Austin, Tx), the U.S. chip- making consortium; “Reliability in

| packaging” will be covered by Paul

Totta of IBM; and Daniel P. Siewiorek of Carnegie Mellon University (Pittsburg, PA) will be the instructor for the section on “fault-tolerant computing.”

| E Bicmos technology

Because it’s so fashionable among designers and manufacturers of mixed-signal ASIcs—even those in- volved in high-speed digital de-

| sign—we should look at some of the

papers in the IEDM session on BiCMOS technology. Once again, IEDM ex- poses us to the dramatic processes and capabilities we can only dream about using—combination CMos and ECL devices with gate delays of 20 or 30 ps. D. Harame, E. Crabbe and other researchers at IBM (Yorktown Heights, Ny) describe a silicon-ger- manium (SiGe) epitaxial base that produces 18.9-ps gate delays at 7.7 mW from the same substrate occu- pied by 0.25-um-geometry CMOS de- vices. Their paper is called “A high- performance epitaxial SiGe-base ECL BiCMOS technology.”

In the same session, T. Lui, G.

| Chin and other researchers at AT&T

Bell Laboratories (Holmdel, Prince- ton and Murray Hill, NJ) show a 0.5-um BiCMOS circuit with 31-ps ECL gate delays and 58-ps CMos gate de- lays. Their paper is called “A Half- Micron Super Self-Aligned Bicmos Technology for High-Speed Applica- tions.”

However, the most practical paper in the Monday session on BiCMOS (as well as one of the most dramatic)

| comes out of experience in smart

power and RF circuits. Authors P. Tsui, P. Gilbert and S. Sun of Mo- torola (Austin, Tx) describe a way to

| integrate 60-V lateral double-dif-

fused MOS (LDMOS) on a BiCMOS sub- strate with 0.5-um devices and fis on

| the order of 26 GHz. With luck,

these structures will contribute to the portable RF transmitters of the near future. a

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ETECHNOLOGY DIRECTIONS INTEGRATED CIRCUITS

Analog Devices courts designers with open architecture DSP

Stephan Ohr, Contributing Editor

he control and manipulation of T analog signals is certainly among the most fruitful uses of DSP technology. But because many DSP components were initially archi- tected as microcontrollers and re- quired extensive programming or coding, traditional analog designers were among the slowest to grasp the potential of this burgeoning technol- ogy. Apart from programming diffi- culties, there is also the issue of price. Many frequency filtering and timing-window control functions can be performed much more cheaply with a fistful of inexpensive analog components.

Manufacturers of DSP components and development tools have tackled these problems head on. They’re im- proving the performance and push- ing down the cost of their compo- nents, while perfecting easier-to-use toolsets. And as a result they’re wit- nessing an exponential growth in the number of applications that take advantage of DsP solutions.

_ H initiative proposed

But the conversion process is far from complete. A recent Computer Design/Indian Forest Research sur- vey of analog and mixed-signal sys- tem designers found that far fewer than 50 percent were considering psP solutions. Many analog design- ers seem resistant to using DSP, and chip-set vendors are taking new steps to convince this group that DSP isn’t just some sort of fancy micro- processor.

Against the possibility that real- world system designers are finding it difficult to choose among compet- ing DsP architectures and vendors, Analog Devices (ADI—Norwood, MA), an acknowledged leader in analog | signal-conditioning and data-con- version technology, has proposed what it calls a Signal Computing | Initiative. Like the cap Framework Initiative talked about by EDA tool | vendors, the Signal Computing Ini- tiative calls for an open architecture

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46 DECEMBER 1992 COMPUTER DESIGN

The increasing bandwidth and precision of psp cores let them be utilized over a wide range of low- to high-end applications, says tis Kun Lin. The majority of these designs, however, are custom projects rather than off-the-shelf drop-in

that lets designers mix and match DsPs, signal-port chips, drivers, and operating systems. Ideally, you can pick and run off-the-shelf compo- nents and algorithms for speech rec- ognition, audio and video image compression, and modem line conditioning.

“Front-end ports geared for audio or telephone can be paired with DsPs from Analog Devices or Motorola,” says David D. French, Analog’s vice- president and general manager. “Nothing is proprietary.”

Anticipating critics who may sug- gest that the Signal Computing Ini- tiative is a response to the domi- nance of competitors’ components— specifically those of Texas Instru- ments (Houston, Tx) and Motorola (Austin, Tx)—Analog Devices an- nounced an impressive series of de- sign wins at DSPx, a new conference and trade show dedicated to digital signal processing, in October. Com- puter maker Olivetti (Ivrea, Italy and Cupertino, CA), for example, uses the Analog Devices ADSP-2111 processor and voice codecs to imple- ment digital voice recording and playback on its Quaderno portable pc. Siemens (Munich, Germany) uses the ADSP-2111 as a speech rec- ognition device for neural networks.

| Lernout & Hauspie (Ieper, Belgium)

and VTech Systems (Hong Kong) have gotten together on a talking multilanguage dictionary using the Analog Devices ADSP-2105, and Digianswer of Denmark will OEM digital answering machines and boards using ADI components. All these manufacturers have endorsed the Signal Computing Initiative.

Bi still a custom business

Yet, the true impact of a Signal Com- puting Initiative may not be felt for some time. It isn’t just that Analog Devices has a smaller number of de- sign wins than its competitors, which makes it a less powerful lobbyist for open systems. The acceptance of the

| initiative may be limited more by the

fact that the largest part of Dsp de- sign has been a customization effort requiring close coupling between sil-

| icon vendor and customer. It’s only

minimally a standard-parts business supported by off-the-shelf compo-

nents and software.

According to Kun Lin, DSP mar- keting manager for Texas Instru- ments, the company with by far the

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CIRCLE NO. 33

EPTECHNOLOGY DIRECTIONS

-

—

largest proportion of psp design wins, the cpsP product line has been the most aggressive in driving down

the costs of psp solutions. (The “c” in

cpsP stands for “customizable.”) “In volume,” says Lin, “cDSsP can be lower in cost than a boardful of sep- arate analog and DSP components.”

INTEGRATED CIRCUITS

The cpspP line offers an ASIC meth- odology in which signal-conditioning components and A-D and D-A con- verters can be combined with C1X or C2X processor cores, versions of the TMS320 architecture, to provide parts with analog inputs and out- puts. The increasing bandwidth and

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48 DECEMBER 1992 COMPUTER DESIGN

precision of the DSP cores, moreover, let them be used over a wide range of low- to high-end applications. But these are hardly drop-in re- placements for analog components. The specialized requirements of disk-drive manufacturers, for exam- ple, militate against the use of stan-

' dard off-the-shelf components. Yet

drive makers are gravitating toward DsP solutions to the problems of head positioning and spin control.

The DsP core provides specialized acceleration and deceleration algo- rithms that ensure greater tracking ability with tighter track densities and shorter seek times. The analog inputs make it easy to read embed- ded servo bursts, while the analog outputs drive power transistors and motor coils. The cost of an integrated DSP solution won’t be competitive with the op amps and filters cur- rently used for this application, but the increased precision, reliability and lack of drift mean that the over- all cost of ownership is very reason-

| able. For this reason, DSP ASICs are | finding their way into a wide variety

of custom applications, including in- dustrial motor controls and digital answering machines.

| Zilog prefers DSP ASICs

Zilog (Campbell, CA) also supports a psp Asic methodology. Its Z89120 modem controller, for example, con- sists of an 8-bit microcontroller, a 16-bit DsP core and data converters geared toward pulse-width modula- tion. The part handles 9,600-bps mo- dem, fax and voice interactions be- tween a telephone line and a computer host.

Bryant Wilder, Motorola’s psp operations manager, sees little need to court analog designs with drop-in solutions to applications currently served by analog components. “There are many applications which will benefit from [the]...programma- bility...precision and reliability of a DsP solution,” he says, “but it’s al- ways better to start with a clean sheet of paper.” Although there are psP chips that sell for less than $3, he adds that “You don’t get a lot for $3.” DsP becomes cost-effective in a design that was meant from its in- ception to offer high precision, reli- ability and programmability.

The improvements in price-per- formance of DSP components, and es- pecially improved bandwidth, pave

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CIRCLE NO. 30

ETECHNOLOGY DIRECTIONS

the way for applications that didn’t previously exist. In addition to suc- cesses in digital cellular telephone applications in Europe (and, in- creasingly, in the U.S.), Wilder points to the use of 56000 products in Sony’s newly introduced 5-4-in. erasable optical disk products. The

INTEGRATED CIRCUITS

56000 in these peripherals controls the focus and tracking of the optical laser. Because of their potential for drift with temperature, analog com- ponents could never provide the de- gree of control possible with a 24-bit psp. “Analog runs out of gas,” says Wilder, “but, with new psp technolo-

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CIRCLE NO. 28

50 DECEMBER 1992 COMPUTER DESIGN

| gies, we have the opportunity to con- vert a $500 or a $1,000 system into | a $50 or $100 board.”

Bl Success at Star

As it turns out, the success of Star Semiconductor (Warren, NJ) in win- ning over analog designers to DSP solutions is related more to its abil- | ity to customize parts for an applica- tion than it is to any low-cost drop-in replacement. While similar to the Motorola 56000 in capabilities (in that it provides 24-bit fixed-point processing), the architecture of Star’s SprocChip is totally customiz- able by the user. Unlike micro- | processors, which need to be pro- grammed, SprocChips can be specifically crafted for analog appli- cations. These chips are like PLDs for analog—the program is the architec- ture. And Star’s pc-based develop- ment tools are intended to make the programming job easy. This start-up company now has an impressive number of design wins among com- munications and audio equipment manufacturers.

These design wins are due more to the ease-of-use of the architec- tural development tools, however, _ than to price or other factors. While the company is working toward a | $25 part, current versions of the | SprocChip are in the $100 range, and they’re targeted toward the same applications that TI and Mo- torola say they can do for $10.

While psp offers innovative solu- tions to the problems of interfacing | electronics to the real world, the de- signer’s preference for custom DSP may seem to negate the multivendor drop-in solutions proposed by Analog Devices. And while “cost-ef- fective” is a part of the company’s vocabulary, if analog design is to be synonymous with “cheap,” DSP ven- dors still have a way to go. |

For more information about the technol- ogies, products or companies mentioned in

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PTECHNOLOGY DIRECTIONS

SOFTWARE & DEVELOPMENT TOOLS

Alliances to speed acceptance of fuzzy logic technology

Tom Williams, Senior Editor s fuzzy logic gains acceptance A as a viable technology for em- bedded control, alliances are starting to form between large mer- chant semiconductor companies and smaller companies that were ex- pressly founded to develop and mar- ket fuzzy logic software and hard- ware. Most of the latter companies are moving from being primarily consulting and custom engineering firms to becoming vendors of soft- ware development tools and dedi- cated fuzzy processor designs. Motorola (Schaumberg, IL), for ex- ample, has formed an alliance with Aptronix (San Jose, CA), which is making the transition from engineer- ing consulting and design to vendor of its new Fuzzy Inference Develop- ment Environment (FIDE) product. FIDE, which will be jointly marketed by the two companies, includes edi- tors for fuzzy membership functions and rule sets, three types of debug- ging tools, a composer tool for link-

ing modules created under FIDE with | other C programs, and assembly

code generators. The current ver-

sion of the product directly supports |

Motorola’s MC6805 and 68HC11 8- and 16-bit microcontrollers. Intel (Chandler, Az) has also ar-

ranged a partnership with Inform |

GmbH (Aachen, Germany and Evanston, IL). Inform offers a fuzzy

logic development system called |

fuzzyTECH. FuzzyTECH supports

graphical editors for the fuzzy rule |

base, as well as for membership func- tions, and it provides an interface for

graphically simulating designs. The | development tool generates C code |

and optimized assembler code for se- lected microprocessors. In collabora- tion with Intel, Inform is supplying a version of fuzzyTECH, Release 3.0, that directly supports Intel’s 8xC196 line of 16-bit microcontrollers.

One of the unique features of fuzzy- TECH is its online editing capability. With a serial line, you can modify the membership functions or rules of a running system through the

graphic editor, and then you can di- |

rectly observe the results in system behavior. Further, the Inform prod-

uct supports the integration into de- signs of neural net technology. This feature may come in handy, given Intel’s recent activity in neural net processors—such as its 80170NX analog neural network chip and Pc- based neural training software.

For initial evaluation, Inform supplies a $199 Explorer version of fuzzyTECH that features limited functionality. You can create sys- tems with 2-input and 1-output var- iables and up to 5 labels (or mem- bership functions) per variable, as well as one rule block with 125 rules. The Explorer outputs C code that can be integrated into some applications.

Bf Hardware/software partnerships Dedicated fuzzy logic companies that have developed designs for processor chips, such as Togai Infra- logic (Irvine, cA) and American NeuraLogix (Stanford, FL), have been contracting with silicon found- ries to produce their designs. But

both these companies have also signed licensing agreements with semiconductor companies for the

| use of their fuzzy processor designs | as core technology.

American NeuraLogix, for exam- ple, has signed a 10-year technology transfer agreement with Samsung

| (Seoul, Korea) that gives the Korean

company manufacturing and use rights to NeuraLogix’s core chip technology. Central to that technol- ogy is the NLX230, a high-speed, low-cost 8-bit fuzzy microcontroller. The NLX230 and its newly en- hanced version, the NLX231, are both capable of about 30 million rule

| evaluations per second and contain

hardware-defined membership functions, fuzzifiers and defuzzifica- tion options. The agreement with

| Samsung is seen as a way to accel-

erate the migration of fuzzy logic into a wide variety of products.

NeuraLogix supplies a software tool specifically aimed at program- ming its processor products. The tool comes with an AT-compatible devel- opment board containing an NLX230. The NLX231 is downward- compatible with the NLX230 but contains more options and can hold more rules.

Togai Infralogic offers a full line of

FIDE_EZ Linker

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\44

7 pstepi

Ea

a a

Aptronix’s Five includes a facility called Composer, which can be used to graphically link fuzzy inference units (rius) to C code modules from existing or conventional applications. This process generates applications containing a combination of

conventional and fuzzy logic code.

52 DECEMBER 1992 COMPUTER DESIGN

Learn the Only Embedded Debugger You Will Ever Need Without Turning the Page

TARGETS:

68xxx, 386/486, R2000/R3000/R4000, Sparc, 88000/88110, Gmicro, V810, more...

C + C++ © Fortran ¢ Pascal

Double click on a variable to create a window that displays its value when- ever the program stops.

Click on a variable to print its value.

Click on a green dot to set

3 a breakpoint. Click on the stop sign to clear the breakpoint.

The program is currently stopped here.

i+ at

struct bag { struct bar *next;

float d[10]; int count; }*Bar;

ct bar *NewBar(count,color) enumcolor color;

enum color {red,orange,yellow,green,blue}color;

Click here to see the object this points to.

Double click here to see this array

0, 1,2,3,4,5.,...

in a new window.

Move the mouse here and type in

| 10<

a new value.

ret = (struct bar *)malloc(sizeof(struct bar));

_ | 57 ¢ ret->next= NewBar(count-1,color); 58 ¢ ret->color = color; ——— = = ¥ = z 5 Click on a function oe | | \ 59 ¢ ret->count = count; | I boi ener e J to display its source code. {\| \60 ¢ for (i=0;i<ount; i++) | 0_NewBar(count= 10,color=orange( 1 )) | | 6laamm ret->d[i] =i; * 1_main( i} 62 ¢ return ret; —— =a! | rs }

Attach to a target with the | "remote" command.

Set a conditional break- point at the current line.

Click “go” to continue (or start the program).

Click register view window.

Click “help” to learn the rest of MULTI.

“reg” to display at =

[stops IL regs at local it pop |

Click “calls” to

display a call

stack window. Click “halt” to

stop execution of the program.

Click “edit” to edit the current function.

Click “assem” to + display interlaced source/assembler.

It’s worth learning MULTI to to fix one bug.

Hosts: Microsoft Windows, 8 Sun-3, DECstation, Unix/386, Motorola Delta, more..

will las i,

se reen Hills ae “SOFTWARE. INC. ¢ $10 Castillo, Santa Barbara, CA 93101 1 Cranberry Hill, Lexington, MA 02173 Tel: (805) 965-6044 ¢ FAX: (805) 965-6343 Tel: (617) 862-2002 © FAX: (617) 863-2633

Copyright 1992 Green Hills Software, Inc. MULTI and Green Hills Software are trademarks of Green Hills Software, Inc. All other trademarks are trademarks of their respective owners.

CIRCLE NO. 34

ETECHNOLOGY DIRECTIONS

SOFTWARE & DEVELOPMENT TOOLS

fuzzy logic software development tools and hardware. Its FC110 fuzzy processor is available as a chip or integrated on board-level products for AT, VME and Multibus. Togai also offers a line of software development tools, of which the centerpiece is TILShell. TILShell is a Windows- based graphical development envi- ronment that lets you edit and debug membership functions and rules. It interfaces directly to pack- ages that generate code for the FC110, MicrorrL code that can be run with an interpreter for a wide selection of 8- and 16-bit micro- processors, and a C code generator. In addition, Togai offers TILGen, a package that uses neural network technology to analyze a system’s in- puts and generate a rule base. Most recently, Togai has intro- duced a core cell technology called FCA (fuzzy computational accelera- tion). The FCA core can be implemen- | ted in a range of sizes, from 8 to 32 bits, and can be used as a stand- _ alone processor, integrated on a chip

Neufuz block diagram

APPLICATION PARAMETERS ee SYSTEM INPUT/OUTPUT DATA

oe

FUZZY RULES AND MEMBERSHIP FUNCTION GENERATOR

NEURAL NET LEARNING

MEMBERSHIP FUNCTIONS

FUZZY RULES

MICROCONTROLLER ASSEMBLY CODE

esas eae Mal

SYSTEM INPUT DATA

Neufuz from National Semiconductor uses the input/output data along with the pa- rameters specified for the system under development to automatically generate fuzzy rules and membership functions—and, ultimately, the application code. The devel- oper works by converging the design on the expected behavior of the system and then verifying it, but he or she won't see the intricate detail of the internal workings.

We Give ( 0 To Our Customers.

Whatever it takes, at Mitsubishi we’ll go the extra mile to help our cus- tomers meet their memory card needs.

That means onshore applications

Our dedication to 110% customer support is why we maintain well-stocked, / onshore inventories, totally automated / shipping services, and inventories available through authorized Mitsubishi Electronics America, Inc. stocking reps and distributors.

engineering, marketing and sales support. It means we'll support your custom card, custom panel artwork and programming requirements, as well as provide cards that meet current PCMCIA, JEIDA

and JEDEC standards.

54 DECEMBER 1992 COMPUTER DESIGN

When it comes to memory cards, we're here when you need us. We follow up. We solve problems. We give 110%.

2. MITSUBISHI

Call (408) 730-5900, ext. 2214. ELECTRONIC DEVICE GROUP

CIRCLE NO. 35

DISTRIBUTED PROCESSING WITH THE QNX® FLEET™ NETWORK.

BECAUSE COMPUTERS WERE MEANT TO RUN TOGETHER.

Maybe it’s not natural to expect a network of microcomputers to

perform like a supercomputer.

With the QNX operating system, it’s not natural to expect anything less.

POSIX AND MORE

Thousands of VARs and OEMs choose QNX for mission-critical applications — from POS to manufacturing to medical instrumentation.

And with good reasons.

Like POSIX compliance.

And real realtime performance. And true microkernel architecture. And message-passing IPC.

Not to mention our technical

support and customer services. Now add “FLEET” to the list.

FAULT-TOLERANT NETWORKING

With most networks,

a hardware failure spells disaster. But not with QNX.

Ifa card or cable fails on

a dual-net FLEET setup, QNX will automatically re-route data through the other network

before you — or your application — can even blink.

LOAD-BALANCING ON THE FLY

For greater throughput, the FLEET network puts all available network hardware to work at the same time. And it will dynamically distribute the load by choosing the best route for the job.

EFFICIENT PERFORMANCE

FLEET uses network hardware to full advantage for maximum throughput. Whether you're running Ethernet for speed (application-level throughput at just under 1 Mbyte per second) or Arcnet for deterministic transactions — or both network cards in the same machine — you can count on FLEET for optimum efficiency.

REALTIME OPERATING SYSTEM

CIRCLE NO. 36

EXTENSIBLE ARCHITECTURE

You can support new networks simply by adding new drivers. And you can start and

stop drivers dynamically,

without even rebooting.

TRANSPARENT DISTRIBUTED PROCESSING

In QNX there’s no difference between local execution and network-remote execution. Which means you don’t need to modify your applications in order to distribute them across

the FLEET network.

To sum up: networking with QNX is fault-tolerant, load-balancing, efficient, extensible, and transparent. But it’s a lot easier

to just say “FLEET.”

Go with the QNX FLEET network. Nothing runs like it.

To find out how your applications can thrive in the QNX environment, call 1-800-363-9001 (ext. 103).

ETECHNOLOGY DIRECT

IONS

SOFTWARE & DEVELOPMENT TOOLS

with a conventional processor core, or put on a chip with custom logic. Different mixes of rule-base and scratch-pad memories can be incor- porated as well.

Togai has entered into two agree- ments, one with visi Technology (San Jose, CA) and another with Hi-

tachi America (Brisbane, CA). The agreement with VLSI has resulted in the first implementation of a func- tional system block (FsB) for fuzzy logic applications. It’s a 12-bit imple- mentation of the FcA technology that’s been dubbed the VY86C500, and it’s capable of some 850,000 rule

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CIRCLE NO. 37

56 DECEMBER 1992 COMPUTER DESIGN

evaluations per second at 20 MHz. The fuzzy FSB can be combined with other microprocessor FSBs to form complete conventional/fuzzy proces- sor units for embedded systems.

Togai’s agreement with Hitachi America covers the use of fuzzy logic on conventional microcontrollers, primarily Hitachi’s H8. It also in- cludes support for training, docu- mentation and hardware evaluation products, as well as for adapting software development tools to use with Hitachi processors.

| Going it alone

The one US. semiconductor vendor that seems to be going it alone is National Semiconductor (Santa Clara, CA). National has set out on an ambitious project to develop fuzzy logic products simultaneously with neural network technology. It will soon be introducing a development tool called Neufuz. As this software technology matures, National plans

_ to migrate it into silicon products.

Neufuz uses neural net learning to non-heuristically generate fuzzy rules and membership functions, at the same time using only the speci- fications of the system—that is, which outputs are expected from what inputs. The neural net learns by converging the inputs and out- puts with the application parame- ters, after which its output is used to generate fuzzy rules and member- ship functions. These are run through a proprietary rule verifier and optimizer and eventually gener- ate assembly code. €

For more information about the technol- ogies, products or companies mentioned in this article, call or circle the appropriate number on the Reader Inquiry Card.

American NeuraLogix

(407) 322-5608 Circle 209 Aptronix

(408) 428-1888 Circle 210 Hitachi America

(415) 589-8300 Circle 211 Inform GmbH

(708) 866-1838 Circle 212 Intel

(602) 554-2374 Circle 213 Motorola Microprocessor Division

(708) 576-7000 Circle 214 National Semiconductor

(408) 721-5000 Circle 215 Togai Infralogic

(714) 975-8522 Circle 216 VLSI Technology

(213) 931-0009 Circle 217

So you think you can

design a better embedded

computer than we can?

MC68LC040

VME Interface

Of course you can. And we'll even help you. With the new MVME162 Embedded Computer.

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Now, would you like your MVME162 with a 68040 CPU (with floating point) or a 68LC040 CPU (no floating point)? VME bus or no bus? One, two, three, or four IndustryPack “modules? Synchronous or Asynchronous serial ports? Ethernet or SCSI? IMB DRAM or 4MB? 512K or 2MB of SRAM? And what other functions would

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fone i en Seine roe ee ree 5 _— ———s I a ee ae a gn rn es rea are ne haere 4 Motorola and the ® are registered trademarks of Motorola, Inc. IndustryPack is a trademark of GreenSpring Computers, Inc. ©1992 Motorola. All rights reserved

CIRCLE NO. 38

ETECHNOLOGY DIRECTIONS

Warren Andrews, Senior Editor ewlett Packard (Colorado Springs, CO)has just joined

4 the growing cadre of work- station makers bidding for the real- time industrial market. It follows closely on the heels of Digital Equipment Corporation, which an- nounced its entry into the realtime

market with a VMEbus-based ap- proach and a POSIX 1003.4-compat-

(RTOS). HP’s announcement last month introduced a whole family of new products coming from its Measurement & Control Systems Division, a new unit that focuses on

the needs of the factory floor, as |

well as control applications in man- ufacturing, aerospace, telecom, and commercial electronics. In ad-

and boards, HP also debuted the HP-RT RTOS for its hardware.

At the center of HP’s thrust is the company’s PA-RISC 7100 processor. (PA stands for Precision Architec- ture.) The 50-MHz version of the chip set lets systems operate at 61 Mips and betters 60 spECmarks in performance. But that’s only part of the story—HP has boarded the vME- bus in a big way, announcing three major VMEbus board makers as com- plementary hardware vendors

bus trade association, VITA, as a se- nior member.

Bf The VME alternative

While there’s been much discussion of Futurebus+ as the latest-genera- tion backplane bus for a variety of applications, including industrial automation, communications and

ported vMEbus for industrial appli-

ber of vendors offering Vo for VME, recent activity within the trade group pushing the bus to higher ley- els of performance should keep it viable for a number of years.

First, the addition of VME64 doubled the effective bandwidth of the bus, and the possibility of using a source-synchronous transfer pro- tocol holds promise for yet another twofold increase in performance.

58 DECEMBER 1992 COMPUTER DESIGN

ible realtime operating system |

dition to industrial workstations |

(CHvs) and signing on with the vME- |

aerospace, it’s interesting that both | HP and Digital have heavily sup- |

cations. Aside from the large num- | |

Now, it looks as if a viable live-inser-

tion technology is available, and pro- |

totypes will soon be up and running. Future enhancements, including the addition of a number of serial lines

to the P2 connector, promise to bring |

VME up to the performance level that’s now the domain of Futurebus+.

While HP is firmly backing VME as its industrial platform, it still hasn’t abandoned its other approaches. In announcing its realtime strategy, the company mentioned a pair of box-level workstations, as well as its 742rt VME board-level product. Both of its box-level products support the EISA bus. One of them, the 745i, has four EISA slots. The other, the 747i, offers a combination with two EISA slots and six vMEbus slots.

The two workstations are binary- compatible with the company’s S700 and most current S800 systems, let- ting them run many applications | currently supported on HP’s UNIX

platform, HP-Ux. These applications | include a variety of specialized man-

ufacturing automation tasks, as well as database applications and office productivity tools.

The company’s major VME offer- ing, however, is the 742rt 6U VME

| architecture, Hp-RT.

Featuring all-front-panel vo, Hewlett Packard’s HP9000 Series 700rt, model 742rt, is a 6U vmebus card that occupies two vme slots. Its 50-MHz np pa-risc chip set gives | itmore than 60 Mips, one of the most powerful vme cpus to date. It includes standard ceu features such as serial and parallel port, Ethernet and SCSI-2 ports, and comes with a run-time copy of HP's latest realtime operating system designed for the pa

COMPUTERS & SUBSYSTEMS

HP debuts VME, realtime solutions

board. Designed as a single-board system, the 742rt takes up two VME- bus slots and boasts one of the high- est performance ratings of any VME CPU, topping off at 61 Mips. It differs from most competitive products in that it offers Ecc memory (8 Mbytes

| standard, with 16, 32 and 64 Mbytes

optional) in place of parity-protected memory. According to HP, this type of memory detects and corrects sin- gle and multibit errors, providing a more reliable system than a parity- protected approach.

The vME card has all Vo coming off its front, as opposed to systems with yo connection off the card itself or off the P2 connector. Like most CPU cards, HP’s 742rt has a variety of built-in Vo, including a pair of RS- 232 ports, a parallel port, Ethernet, and SCSI-2.

B HP-RT completes the picture The 742rt includes a run-time li- cense for HP’s realtime operating sys- tem, HP-RT. Unlike Digital, which se- lected a third-party rTos, Wind River’s VxWorks, to modify for its processor, HP has built its own oper- ating system.

Designed to be posix 1003.1-,

INTRODUCING THE TP810V TADPOLE’S HIGH-PERFORMANCE COMPUTING ENGINE FOR REAL-TIME APPLICATIONS

200 MIPS and VME;-64

Real-Time Performance.

No Compromises.

When we designed the TP810V, we approached it with total system performance in mind. With state-of-the-art microprocessors, high-speed memory, the latest generation I/O components, VME-64 and optimized real-time software, nothing gets in the way of information throughput on the TP810V.

Issuing up to 2 instructions on every clock, Motorola’s 88110 Symmetric Superscalar™ RISC microprocessors provide the TP810V’s horsepower. With dual 50 MHz 88110

3 A

microprocessors”, the TP810V achieves overall system performance of up to 200 MIPS/ 200 MFLOPS — that’s an impressive $50/MIPS.

Memory options include 1 MB of high-speed synchro- nous SRAM with a sustained bandwidth of 228 MB/s and an expansion board with up to 128 MB DRAM. The TP810V accesses the additional DRAM at sustained on-board memory speeds of 133 MB/s.

And because cache coherency is essential for

Computing Without Compromise

p

D

maintaining

performance in multiprocessor systems, we've built in bus snooping support — even for the VME-64 interface.

The TP810V uses the latest in controller technology to eliminate common I/O bottlenecks: you can choose from two standard I/O modules with a 32-bit Ethernet controller and either one or two Fast and Wide SCSI-2 controllers. If neither of these options fit your system requirement, we'll design a

O

CIRCLE NO. 39

custom module to your specifications.

To complete the system, the TP810V supports Integrated Systems’ pSOSystem™, the modular real-time operating system with transparent multiprocessing capability. And with high-level language compilers readily available for the 88110 microprocessor, you can shorten your product development cycle without sacrificing performance.

If you're looking for a real- time computing engine with superb overall system perfor- mance at a great price, take a look at the TP810V. We think you'll like what you see.

Call Today For A Free Brochure

800-232-6606

FAX 512-219-2222

“Single processor TP810V models are also available.

ETECHNOLOGY DIRECTIONS

COMPUTERS & SUBSYSTEMS

1003.4- and 1003.4a-compatible, HP- RT is designed from the ground up to provide hard realtime capability tuned to the HP PA-RISC platform. A native POSIX application program- ming interface (API) is implemented for system calls, realtime extensions and process threads. The os also incorporates some of the best UNIX features, including protected ad- dress spaces, multiprocessing and graphical user interfaces, into HP-RT.

In addition, HP-RT can be scaled to balance memory and performance requirements. With a small kernel, overhead is kept to a minimum, and optional services can be invoked as required. The OS complies with the POSIX 1003.1 standard, and it follows the posix 1003.4 draft 9/10 for real- time extensions, as well as the PosIx

1003.4a draft 3/4 for process-level |

threads. POSIX compliance has re- mained an elusive thing for realtime extensions because of the rapidly changing drafts. Some vendors have elected to use a particular draft, such as draft 4, rather than continue to shoot at a moving target. (The

current version, which is under- | going the approval-or-rejection cy- |

cle, is draft 10.) The HP-RT includes many SVID/BSD commands and sup-

ports C, ANSI C, C++, and PA-RISC as- |

sembly.

B Third parties party on

While both Hp’s box-level worksta- tion products have at least some EISA

capability, the company’s support of

VMEbus is emphasized with an in- dustry-leading cPpU, membership in industry trade groups and its third- party agreements. The latter in- clude arrangements with the cmc Network Products Division of Rock- well International (Santa Barbara, CA), SBE (Concord, CA) and VMIC (VME Microsystems International— Huntsville, AL).

According to Hewlett Packard, cmc has been selected as a CHV to provide Ethernet and FDDI VMEbus local-area network connectivity for its realtime industrial workstations. cmc plans to work closely with HP to supply the necessary drivers for both HP’s realtime and UNIX operat- ing systems.

SBE will be offering HP’s OEMs and integrators its eight-port VCOM-34 X.25 controller, with eight high- speed serial ports in a single VMEbus slot. Its eight full-duplex, inde-

pendently programmable serial channels can transmit and receive asynchronous, X.25-compatible HDLC and bisynchronous protocol data at E1 (2.048 Mbps) rates. sBE’s VCOM-34 card includes an on-board 68030 processor to ease the burden of the HP PA-RISC processor.

The company will also provide its VPU-25 intelligent vo controller to handle a variety of 0, memory and custom options. The board is meant for OEMs requiring a high-perfor- mance interface between VME sys- tems such as a mini/super minicom- puter and wide-area networks or other applications requiring high- speed point-to-point data transfer. Serial interface modules let each port be separately configured for EIA-232-C, EIA-422, EIA-449, EIA- 530, X.21/V.11, or V.35 standards.

VMIC will offer a variety of /O prod- ucts, including host adapters, VME- to-VME links, repeaters, reflective memory, digital and analog vo and synchro/resolver 1/0. Transition pan- els, power supplies, chassis, and other supporting products will be offered as well.

With both up and Digital making firm stands in favor of VME in the industrial-control and factory-auto- mation arena, it seems that the VME standard is likely to continue its dominance in this area. With the inclusion of HP’s PA-RISC, every major RISC architecture now has strong VME support—with the exception of IBM’s RS/6000. SPARC is represented by, among others, Force, Themis and Tronics. «

For more information about the technol- ogies, products or companies mentioned in this article, call or circle the appropriate number on the Reader Inquiry Card.

CMC

(805) 968-4262 E Circle 218 Hewlett Packard (U.S.)

(800) 637-7740 Circle 219 Hewlett Packard (Canada)

(800) 387-3867 Circle 220 SBE

(800) 347-2666 Circle 221 VMIC

(800) 322-3616 Circle 222

60 DECEMBER 1992 COMPUTER DESIGN

Looking for more than a

sales pitch at Buscon West?

When you visit Radstone Technology at Booth #826 this February, you'll meet more than just a sales rep.

We think Buscon should be a source for information, and exchange of ideas, on the technology and the industry. And, most of all, solutions to your problems.

Come talk to the:

e President

e V.P. Sales

¢ Director of Marketing

e Engineering Manager

e Marketing Manager, Product Technology

¢ Senior Applications Engineers

¢ Regional Sales Managers

Oh yes, and lots of very knowledgeable sales reps too!

So if you’re looking for some- one you can really talk to about VME, visit Radstone at Buscon/93-West. We'll make it worth your while.

ate RADSTONE

T: EG, BEN OnEL@ Gay

Booth #826

Dn

BUSCON/93-WEST

for Any VME Board!

The Radstone HS-1

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re eos tO 7

20: @®

Count on Radstone to deliver real world solutions to all your VME system needs. Need to insert or remove a board without powering down the system? The HS-1 is ready today to add this live insertion capability to your existing VME boards. No smoke, mirrors or complications. Just a clean, clever solution.

¢ Works with any standard VME board and backplane

¢ Lets you use off-the-shelf hardware to configure your system

¢ Provides controlled ramp up/down of power rails

¢ Assures complete isolation of the VMEbus from the board during power up/down sequences

e Automatically links daisy chain signals when a board is absent

e Sub-nanosecond delay times for all pertinent VMEbus signals

Radstone’s done it again... this time with live insertion. Let us do it for you. Call or write for the details.

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CIRCLE NO. 40

BUSCON/93-WEST See us in booth #826

T EC H NOL ONG ¥

ETECHNOLOGY DIRECTIONS

COMPUTERS & SUBSYSTEMS

*

Image processing gets price-performance boost

Warren Andrews, Senior Editor ecause most image processing applications are too narrow

Be for sales volume to reach even

a minimum payback level, solutions have remained expensive and pro-

prietary, or they've been composed | of large and bulky collections of stan- |

dard and custom boards assembled

to satisfy a specific application. Now, next-generation hardware

from Datacube (Danvers, MA) takes

advantage of finely tuned asic tech- |

nology to cut size and cost while sig- nificantly boosting performance. At the same time, the modular architec- ture of the hardware, based on a tech- nology called vsiM (Virtual Surface Image Memory), lets it accommodate a broad variety of applications while using relatively standard, low-cost components. VSIM is similar in ap- proach to the company’s Max- Video 20 board, but the new module has a far larger mem- ory capacity, as well as on- module processing circuitry.

At the heart of each module is a 225,000-gate Asic Datacube calls the D52. Not only does it manage image pipelines and perform many image process- ing tasks, but it lets the system use relatively inexpensive standard DRAMs in place of more costly multiported video RAMs. Each module can support multiple 40-MHz image pipe- lines and virtual memory, and each includes integral ALU, crosspoint, look-up table, and statistics.

a Development and target The modules will be the heart of a new MaxVideo vMEbus board that Datacube will in- troduce early next year. A fol- low-on to the MaxVideo 20, it will be known as the Max- Video 200. Datacube has al- ready released the product’s development platform, the Maxtp, which includes the new board, and will be availa- ble this month.

The development platform comprises a 5-slot VMEbus backplane; a Motorola

MVME167 68040-based cPU;

a MaxVideo 200 with a full comple- ment of modules and 24 Mbytes of on-board virtual image memory; and Lynx’s realtime operating sys- tem, Lynxos, with X-Windows and Motif; and a scsi hard disk, all in- stalled in a compact enclosure. In addition, MaxtTp provides a tape backup unit, keyboard and mouse. The MVME167 supplies many of the | housekeeping functions and pro- | vides industry-standard serial and parallel ports, as well as support for | Ethernet, scsi and video 1/0. MaxTp is designed to be a superset of what- | ever target system a particular ap- plication calls for.

“We selected Lynxos,”

says

Datacube marketing services man- ager David Wright, “because it has | the look and feel of Sunos, with |

which many developers are familiar. It also provides modular services so that developers can select as little as a basic kernel, or the entire Os, or only as many services as are re- quired.”

The object of the development/tar- get environment is to let you assem- ble an application using the hard- ware platform along with the company’s software tools, which in- clude an interactive graphical user interface and a library of acceler- ated image-processing functions called sm@L (Standard Imaging Layered Library).

picir (Datacube’s Interactive Graphical Imaging Tool) is one of the software tools, comprising an inter- active X-Windows- and Motif-based application that helps you quickly develop image-processing code. It eliminates lengthy editing and compiling cycles by letting you simply point and click on desired image- processing functions.

And when combined with SILL, DIGIT helps you develop and check high-performance C-callable functions and com- plete applications in an inter- active environment without having to recompile at each stage. SILL and DIGIT are lay- ered on top of, and are com- patible with, Datacube’s Im- ageFlow language for pipelined processors.

The object of MaxTp is to supply a full, rich develop- ment environment from which components can be added to an economical, high- performance target system. Target systems can be ROM-, disk- or network-based and can range from simple sys- tems with few operating ser- vices and peripheral devices to complex hardware systems with all os features.

The vsim and the D52 at its heart are the brainchild of Datacube’s principal design engineer, Shep Siegel, who says “It's the first 40-MHz image processor on a single chip.” The asic not only speeds data on and off the new module, but also provides a large virtual memory and in- tegral on-chip processing functions, permitting the use of relatively inexpensive DRAM.

B ASIC is key

The third generation of Datacube’s MaxVideo tech- nology, the D52 and its asso- ciated vsIM technology ad-

62 DECEMBER 1992 COMPUTER DESIGN

As designs become more complex and time-to-market decreases, new tools are needed to keep up with the technology.

OrCAD’s new line of products offer the same user interface that has made them the world's most popular EDA tools, plus unprecedented speed and capacity.

Easy enough to get a single “A” size design done quickly, powerful enough to produce complex, 200 layer hierarchical designs. SDT 386+, designed to take advantage of 32 bit data structures and addressing on 386/486 computers, includes over 20,000 unique library parts in 60+ libraries, 30+ netlist formats, and much more.

The best tool on the market for writing logic for programmable chips (PLAs, PLDs, GALs, etc.). The compiler accepts seven forms of input including Boolean equations, truth tables, state machine procedures, logic synthesis; even schematics from Schematic Design Tools 386+. Output can be accepted into OrCAD's digital simulator for accurate simulation of designs with multiple programmed PLDs.

This timing based, 12 state, event driven simulator with support utilities allows easy simulation of digital designs of up to 200,000 gates. The graphical interface will be familiar to any designer who has worked with a logic probe. Thanks to OrCAD's intuitive ESP Framework, Digital Simulation tools 386+ works seamlessly with other OrCAD products.

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CIRCLE NO. 41

BTECHNOLOGY DIRECTIONS

COMPUTERS & SUBSYSTEMS

vance the company’s resolution-in- dependent, region-of-interest (ROI) concept, providing faster pipelines, a virtual memory and the capability to perform a variety of processing steps on each stage of the pipeline.

“The D52 is fabricated on a 225,000-gate sea-of-gates array in

0.8-Lum CMOs capable of handling in- put, processing and output at 40 MHz,” says the company’s principal design engineer, Shep Siegel. “It’s the first 40-MHz image processor on a single chip.” With the capability to handle multiple frame memories,

and with its own ALU, LUT and other

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The flexible architecture lets mul- tiple VSIMs be wired in parallel, re- sulting in even greater pipeline bandwidths. Because much of the processing can now take place in the 40-MHz pipeline of the D52 chip, it’s possible to provide functions that are difficult, if not impossible, to im- plement at the board level, because of buffer delays and interconnect capacitance.

By implementing virtual memory, the system can support image ar- rays that are larger than the amount of physical memory availa- ble, and so it can easily handle com- plex applications. The D52 can ad- dress a virtual memory space of up to 96 Mbytes. In addition, vsIm mod- ules can handle 40-Mbyte/s block transfers into and out of the module simultaneously.

B Diverse applications

Datacube has found wide-ranging applications for its technology, from image-enhancing systems for re- mote inspection of objects in hostile environments to controlling robotic equipment in food-processing opera- tions. The company’s systems are even used in high-level prepro- cessing applications for images that will later be worked on with high- powered DsP or even Cray-type su- percomputers.

“But the bottom line,” says Siegel, ‘is that for image-processing tech- nology to become more prevalent in more applications, costs are going to have to drop significantly from their present levels and systems are going to have to be more compact.” This

has to happen at all levels of the system, from the hardware and soft- ware development right down to the rudiments of power supplies and packaging. re

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For more information about the technol- ogies, products or companies mentioned in this article, call or circle the appropriate number on the Reader Inquiry Card.

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CIRCLE NO. 42 64 DECEMBER 1992 COMPUTER DESIGN

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CIRCLE NO. 43

BTECHNOLOGY DIRECTIONS

CAE/CAD TOOLS

No agreement on best way to link digital and analog simulators

Mike Donlin, Senior Editor he topic of mixed-signal simula- |

T tion often causes heated debates among EDA vendors. Simply | stated, the arguments revolve | around which linking algorithms are | best—lockstep, leapfrog or back- plane. In all of these environments, digital and analog simulators per- form separate tasks, each simulat- | ing the portion of the circuit that it’s assigned. Usually, the faster digital simulator has to wait for the slower analog engine to perform its duties.

Whenever one simulator needs to pass information to the other, the communication is done through a software interface that links the | two. This algorithm can be part of a simulation backplane that lets mul- tiple simulators communicate, or it can be achieved by a simulator-spe- cific algorithm that links the chosen simulators tightly together.

| Backplane vs leapfrogging

Proponents of the backplane ap- proach argue that having a range of choices for simulation tasks lets you select the tool that’s best for the job. They say that no one algorithm is suited to simulate the different com- ponents in a complex circuit, and that accuracy is often sacrificed for performance when a simulator is too generic. An algorithm for a switched capacitor filter, for example, won't | handle anything else, but it’s accu- rate because it’s tailored to simulate one device and is faster than Spice.

EDA vendors such as Cadence De- sign Systems (San Jose, CA) and Mentor Graphics (Wilsonville, or) use the backplane method, which integrates digital, analog and mixed-signal algorithms into a ho- mogeneous environment. But there are problems with such an ap- proach—namely, in timing the events of multiple simulators to re- flect the real-world behavior of a circuit as its digital and analog com- ponents interact.

“Many people who use the back- plane method set up a time-based intercommunication,” says David | Smith, vice-president of engineering | at Analogy (Beaverton, oR). “This

means that each simulator works within a time slice—say, of 1 ns—to perform a function. That’s well and good, but with that approach, events aren’t necessarily simulated when they actually happen in the circuit. They happen plus or minus an error term, which makes the simulation efficient but lowers accuracy. If you make the time slice very small, ac- curacy goes up, but efficiency goes down because there’s a lot more event traffic on the backplane.” Analogy solves this problem by

avoiding the backplane approach al- together and using its Calaveras al- gorithm to tie its analog simulator, Saber, to the Cadat digital simulator from Racal-Redac (Mahwah, NJ). The tools are linked together in a master/slave configuration, with the user deciding which simulator will assume the dominant role. The sim- ulators run concurrently and are synchronized via the Calaveras al- gorithm, which lets the analog sim- ulator go beyond a digital event and run at full speed. If a digital event

LOCKSTEP SYNCHRONIZATION

ANALOG |

Mixed-signal algorithm comparison

DIGITAL |

T4

LEAPFROG SYNCHRONIZATION

ANALOG

DIGITAL

i T2

T6

STEP BACK AND RESTART

GenRad’s Shado simulator uses the lockstep algorithm for synchronization of analog and digital simulation engines. With this approach (top), the digital engine is the master, the analog the slave. At time step t0, the analog engine is asked to simulate up to the time of the next event in the digital queue, t1. After, the digital engine simulates the event at t1, resulting in a new scheduled event at t2. The analog engine now tries to simulate up to t2, but finds an event occurring at t1 + a, short of t2, which will affect the digital simulator. It then stops at t1 + a and passes control back to the digital engine, which reschedules and simulates the event at t1 + a. GenRad compares this to the leapfrog algorithm (bottom), in which the faster digital simulator is allowed to run ahead of the analog engine. If the digital simulator arrives at time t4 with an event to pass to the analog simulator, it waits until the analog engine reaches t4 to transmit data. If the analog engine is at event t2 when the digital event t4 occurrs, the analog engine finds an event relevant to the digital engine, and the digital simulator steps back to t2 and restarts.

66 DECEMBER 1992 COMPUTER DESIGN

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CIRCLE NO. 73

ETECHNOLOGY DIRECTIONS

CAE/CAD TOOLS

Analogy’s Saber analog simulator can use synthesized behavioral models to shorten simulation times. The behavioral model of a switched capacitor filter (blue line) pro- duced from Saber’s model synthesis runs over 250x faster than the equivalent primi- tive circuit representation. The model closely correlates with the actual device output (yellow line) over the entire operating range.

occurs that will influence the analog circuitry, the analog simulator rolls back and resimulates.

“This approach is different than some mixed-signal simulators that backtrack,” Analogy’s Smith ex-

plains. “Those simulators throw out |

the last analog values computed and recompute with the digital event as the next time step. This wastes valu- able cpu time because it throws out previously computed solutions. The roll-back algorithm, on the other hand, doesn’t throw away the infor- mation it’s already calculated. It

knows, by the mathematics of calcu- |

lating the solution at the end point, all the solutions along the curve from the previous time point. In- stead of throwing out the current solution and starting over from the previous event, then, it simply rolls back to the time where the event occurred and uses that value with- out recomputing the whole event.” Critics of this approach say that any backtracking wastes CPU time and is inefficient. “The leapfrog ap- proach is memory-intensive and ex- pensive in Cpu time,” says John

Palmer, mixed-signal product man- |

ager at GenRad (Concord, MA). “With that approach, the faster dig-

ital simulator arrives at an event and waits for the analog simulator. But if the analog engine determines that an event relevant to the digital engine needs to be transmitted across the A-D interface, then the digital engine must step back and restart. This means that the fastest engine must store large amounts of event history, which uses a lot of memory, and must constantly load and reload data, which is expensive in CPU time. In general, leapfrog al- gorithms only offer a benefit if the analog and digital engines run on separate cpus, and even then, they’re very circuit-dependent.”

Bf GenRad introduces lockstep

GenRad’s recently released Shado mixed-signal simulator uses a lock- step algorithm to tie its digital sim- ulator, HISIM, with an analog simula- tor, Eldo, from AnacAb, a German company with offices in Fremont, CA. At any given time step, the analog engine is asked to simulate to the time of the next event in the digital queue. After doing so, the digital en- gine is free to simulate to the next event. If the analog simulator ar- rives at a solution that will affect the digital simulator, it passes control to

| the digital engine, which simulates

up to the event at which the analog engine stopped, using the new infor- mation computed by the analog sim- ulator. GenRad claims that this eliminates a lot of the inefficiency associated with leapfrog algorithms.

“Td have to take issue on the effi- ciency question,” argues Analogy’s Smith. “Because with the lockstep

| approach, the overall simulation

speed depends on the slower of the two engines—namely, the analog. It’s true that there’s a cost for rolling back, but if you do a statistical anal- ysis, you'll find that, for many cir- cuits, that doesn’t happen very of- ten. When you do have to roll back,

| our algorithm lets you save un-

changed data, so the recomputation is reduced. I guess if your circuit behaves in such a way that every digital event affects an analog event, then lockstep would make sense.”

Proponents of the backplane ap- proach say that, while simulation speed and accuracy are important, the real issue is flexibility and ease of use. “We think it’s important not to lock your design to any one or two simulators,” says James Spoto, vice- president of R&D at Cadence. “By keeping a simulator environment open, you can pick different levels of simulation and tie them together hierarchically, depending on the level of detail you need. That means you could use every level of simula- tion, from behavioral- to circuit- level, and tie them together through one user interface.”

Regardless of the claims and counterclaims, however, most ven- dors agree that the real key to choos- ing a simulator is knowing what youre going to simulate. Each of these methods has drawbacks in speed, accuracy or ease of use—and each has strengths in the same

| areas. The real winner will be the

one best suited to your circuit.

For more information about the technol- ogies, products or companies mentioned in this article, call or circle the appropriate number on the Reader Inquiry Card.

Analogy

(503) 626-9700 Circe 225 Cadence Design Systems

(408) 943-1234 Circle 226 GenRad

(408) 432-1000 Circle 227 Mentor Graphics

(800) 547-3000 Circle 228 Racal-Redac

(800) 526-0680 Circle 229

68 DECEMBER 1992 COMPUTER DESIGN

COMPASS Is ALL You NEED. | : =

SILICON

VERIFICATION

ASIC Abyss EDIF Ravine

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Performance Plateau Array Arroyo =m * i > —-

The path to top- most integrated top-down ASIC So chart your course today. down design can be solution in the industry, from first For more information, please anything but straight —_ concept to first silicon. Supporting circle the reader number, call and narrow. And even the largest and most complex (800) 433-4880, ext. 7097 or fax once you get off track, you can get designs that require a million gates your request to (408) 434-7977. into all sorts of trouble. The ASIC and more. wilderness is littered with good COM PA SS point tools that somehow fail to Simply put, we save you time. Design Automation provide an integrated solution. Starting with an easy-to-use 1865 Lundy Avenue wfcitatad ical HDL sad San Jose, CA 95131 integrated graphica anc Tel: 800-433-4880 COMPASS’ Design Automation synthesis environment through Fax: 408-434-7977 knows all about the rules of the comprehensive cell-based and road. That's because we’ve been gate array libraries. And all the Caution: ASIC design may be hazardous to your health. 2 Design delays due to poorly integrated tools may have down it more than any other EDA automated tools you need to a detrimental effect on your career. COMPASS assumes 4 i = no responsibility for those who fail to follow our path to company. We've developed the move on down the design road. Silicon Success.

© 1992 COMPASS Design Automation, Inc. COMPASS and the COMPASS logo are registered trademarks of COMPASS Design Automation, Inc

CIRCLE NO. 44

ETECHNOLOGY DIRECTIONS

ASICs & ASIC DESIGN TOOLS

EDA vendors push to boost top-down design productivity

Barbara Tuck, Senior Editor

ith real technological in- | novation apparently stale-

mated, suppliers of design automation tools are zeroing in on business opportunities that fall under the category of services. Vendors have discovered that it takes more than sophisticated toolsets to increase productivity with an HDL- and synthesis-based top-down design methodology. It also takes libraries that can be quickly characterized to the latest processes, a strategy for design reuse, and consulting services.

When Compass Design Automation (San Jose, CA) re- cently announced the com- mercialization of its physical layout libraries of low-level components—the first such of- fering from a major EDA vendor that provides foundry flexibil- ity and support for multiple toolsets—Dan Skilken, world- wide product marketing direc- tor said, “Commercial librar- ies are a bit of a change for the EDA industry. We see it as a more complete solution, one that will let the industry focus more on productivity and value added.” The Compass Liberty Series of gate-array and standard-cell libraries and compilers for CMOS ASICs and AssPs for example is inte- grated with the Compass ASIC Navigator top-down design system.

Bf Trend toward library sales?

What is the company’s ratio-

nale for going into the library

business? “Ic designers and sup- pliers need more from EDA compa- nies than good design tools to suc- cessfully respond to today’s market pressures,” says president Dieter Mezger. “To keep pace with rapid advances in production capability and design complexity, they require a robust set of library products that provides a solid foundation on which to build new and more advanced de- signs. This trend toward library

70 DECEMBER 1992 COMPUTER DESIGN

commercialization in the 90s closely parallels the acceptance and prolif- eration of commercial CAE and CAD tools in the late ’70s and ’80s.”

The Compass libraries include schematic descriptions, functional models, physical layouts, footprints, simulation models, and icons for low-level library elements. Also available are RAM, multiplier and

Sierra Semiconductor uses the Compass physical layout libraries and compilers in the design of its DSP-based communications chip sets, which integrate voice, fac- simile and data functions. Andy Varadi, vice-president of R&D at Sierra (seated at left), discusses the compiled datapath layout (on screen) for the company’s new V.32 modem chip with design team members Neil Becker and James Tan. “Using Compass digital libraries enables us to spend more time on what we’re unique at—analog and mixed-signal design,” Varadi says.

datapath compilers. After a foundry is selected, Compass uses automated tools and techniques to generate tim- ing models and layout for a specific set of design rules. On average, ac- cording to Compass, the customiza- tion of a subset of the full Liberty Series takes six to ten weeks. As part of its customization services, simula- tion models are generated for most popular simulators. Both VHDL and Verilog are supported.

Will semiconductor vendors em- brace the concept of physical layout libraries being sold by EDA vendors? For fabless semiconductor vendors such as Sierra Semiconductor (San Jose, CA), vice-president of R&D Andy Varadi says that the Compass li- brary service is useful. “Using Com- pass digital libraries lets us spend more time on what we’re unique at—analog and mixed-signal de- sign. We can differentiate ourselves in a new dimension,” he says.

Although Sierra’s been using Compass libraries extensively, it’s been doing so on a contractual basis rather than purchasing the libraries outright. Now that Sierra is buying Compass general-pur- pose libraries that can be tar- geted to any silicon vendor’s process, Varadi says that “We have a greater degree of free- dom. We didn’t have foundry flexibility before. Now we can change process or vendor, and we can move products from one process to another by re- characterizing and resimulat- ing.”

For semiconductor compa- nies with in-house fabs but not much asic technology, the Compass libraries may pro- vide an opportunity to get into the ASIC and ASSP businesses. For others, the libraries could augment current offerings or save characterization time. Li- brary users can also leverage their investments through de- sign reuse.

I Design reuse a goal

The methodology, tools and re- lationships enabling smart reuse of designs is the focus of anew business segment called DesignWare at Synopsys (Mountain View, CA). Intel- ligent design reuse and the consequent leveraging of in- dustrial intellectual property will yield the productivity required to re- main competitive, according to Syn- opsys, which claims that previous strategies for design reuse haven't taken advantage of synthesis as an enabling technology and VHDL as the worldwide language standard. “VHDL gives the practical promise of being the standard for capturing and describing everything,” says Aart de Geus, Synopsys’ senior vice-presi-

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ETECHNOLOGY DIRECTIONS

dent and chairman of the board.

To be available by year’s end, the first two design-reuse products from the Synopsys DesignWare division are Synthetic Designs, consisting of off-the-shelf synthesizable compo- nent libraries, and software called DesignWare Developer for designers wanting to capture their own syn- thesizable and reusable modules. Both are integrated with the com- pany’s Version 3.0 high-level design tools—vHDL System Simulator, De- sign Compiler and Test Compiler.

Synthetic Designs are technology-

independent, parameterized librar- ies of commonly used functions such as ALUs and multipliers that have been preverified with the Synopsys VHDL simulator. These functions can be instantiated in a VHDL or Verilog description or inferred from HDL op- erators. The user configures the Synthetic Design library component for a particular system design by supplying specific parameters and compiling to a target technology. The Synopsys synthesizer then opti- mizes for the context of the sur-

72 DECEMBER 1992 COMPUTER DESIGN

The Synopsys DesignWare synthesis-based design-reuse strategy permits the reuse of existing designs through automatic selection based on design constraints or by manu- al selection of a component through a menu-driven interface. In this photo, the menu for selecting a Synthetic Designs library family is shown (top left), and the desired component within that library family may be selected (bottom left). The existing de- sign is shown with multipliers (yellow), subtracters (pink) and adders (red).

ASICs & ASIC DESIGN TOOLS

rounding system, choosing appro- priate drives and loads.

If you want to build your own inventory of reusable modules tai- lored to your particular design re- quirements, you can use the new DesignWare Developer to create, manage and protect your propri- etary design data. The software gives you a way to key and encrypt designs that can then be distributed to users while intellectual property is safeguarded.

Harvey Jones, Synopsys presi- dent says, “We expect third parties

and end customers to use Design- Ware Developer to share their intel- lectual property with their leading customers and with the general

(Munich, Germany) to provide through the DesignWare program a wide range of system-level models. Also, Synopsys, Texas Instruments (Dallas, Tx) and Comdisco Systems (Foster City, cA) will be focusing on optimizing design productivity us- ing core DsP architectures.

B Hands-on training

To ensure productivity for those adopting VHDL-driven top-down de- sign, Mentor Graphics (Wilsonville, OR) has opened several design cen- ters in the United States, Japan and Europe and has teamed with leading ASIC and FPGA vendors, as well as workstation vendor Sun Microsys- tems, in a worldwide training pro- gram called SmartStart. Mentor’s vice-president of corporate market- ing, David Chen, says, “In the past, engineers have been reluctant to transition to a top-down methodol- ogy because the industry didn’t offer a solution with the level of integra- tion, support or training necessary to make the change. The SmartStart program offers a complete solution consisting of software, hardware, silicon fabrication, and support ser- vices to ensure that customers meet

| time-to-market goals.”

During SmartStart training, you get the hands-on experience of tak- ing a design from VHDL to layout. Fujitsu, st Logic, Mitsubishi, visi Technology, and Xilinx have teamed with Mentor to provide a fully qual- ified and endorsed design flow within Mentor’s Version 8.0 design environment. Each of these vendors is offering design kits based on Men- tor’s Advanced Modeling Process (AMP) ASIC modeling technology to support the company’s recently an- nounced vVHDL-based, fully inte- grated, top-down toolset called De- sign Solver. Mentor’s System-1076

| VHDL simulator will fully comply | with the IEEE 1076 specification by

year’s end. cd

marketplace. As our customers im- plement increasingly complex sys- tems in silicon, the ability to reuse design data will provide the reduc- tion in design time required to re- main competitive.”

To help you decide on the appro- priate system architecture to target,

| Synopsys has entered into a part- | nership with Compiled Designs

For more information about the technol- ogies, products or companies mentioned in this article, call or circle the appropriate number on the Reader Inquiry Card.

Compass Design Automation

(408) 433-4880 . Circle 230 Mentor Graphics

(800) 547-3000 Circle 231 Synopsys

(415) 962-5000 Circle 232

—_

Phanks

for the memories...

At this time, we wish to extend our good wishes for the season and a happy and a healthy New Year, on a personal as well asa business level. You — our readers and advertisers — our friends — helped make 1992 a spectacular and memorable year for all of us at Computer Design

and Military & Aerospace Electronics.

Thanks — and best wishes for a terrific, memorable and profitable 1993.

Militar y&Aerospace COMPUTER Technology Bist Asicienic8. siRurHRRs-DONN Nevsttivs Cesc DESIGN

PENNWELL PUBLISHING COMPANY * ONE TECHNOLOGY PARK DRIVE, WESTFORD, MA, 01886 * 508-692-0700 * FAX 508-692-7780

CIRCLE NO. 46

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CIRCLE NO. 47

FPGA vendors turn

their attention to tools

In the face of stiff competition, FPGA vendors are enhanc- ing proprietary tools, enlisting third-party support, adding text- based entry methods, and backing standards.

fe ler GemPrree Sent Tee Berar etme tee

Barbara Tuck, Senior Editor

W.. FPGAs such hot items,

silicon vendors have had a cap- tive audience. In concentrating on silicon, however, FPGA ven- dors haven’t always delivered toolsets that were easy to use or boasted good results. But as more and more vendors enter the marketplace, a competitor with tools that fail to route a part or whose entry methods don’t include VHDL is at an ever greater disadvantage. As a result, FPGA vendors are finally focusing on creating solutions for users.

To satisfy the demands of electrical designers such as Fred Rakvica at Kodak (Rochester, Ny) for interactive place-and-route software, Actel (Sunnyvale, CA) just announced its Action Logic System (ALS) Release 2.2. With interactive placement and incremental place-and-route, ALS 2.2 will be available next quarter for X-Windows-based workstations. Rakvica, who'll be glad to finally have some control over placement, is using nine Actel 1280 FPGAs in a 30,000-gate project, an enhancement for Kodak’s photo cD program.

B interactive placement

Although Actel has always stressed automatic place-and-route as the strength of its design system, director of marketing Andy Haines acknowl- edges that the extra knowledge a seasoned FPGA designer such as Rakvica has can be important in pushing performance. “With ALS 2.2,” he explains, “users will be able to select the exact degree of control they’d like to have over their FPGA designs.”

The interactive placement feature lets you manually fine tune the results of automatic place-and-route by viewing, moving and editing the location of Actel logic modules; to do so you use ALS 2.2’s graphical interface with icon commands. You can also rely on the automatic features of the software to optimize a design incrementally, without disrupting the placement or disturbing timing optimization. On top of all this, ALS 2.2 offers improved macro modeling for up to 25x faster simulation speeds.

Newcomer Concurrent Logic (Sunnyvale, CA) wooed away Actel user Tom Minnis, senior project engineer at Larse Corp (Santa Clara, CA), before Actel introduced its improved toolset. (Larse manufactures communications pro- ducts.) Though Minnis’ FPGA choice was ultimately based on silicon, (accord- ing to him, Concurrent’s CLi6000 Series is the only FPGA with the freedom

COMPUTER DESIGN

Actel’s Action Logic System 2.2 uses a Motif-compatible X- Windows interface and features stan- dard X-Windows menus, a list box (upper righthand text box) that shows all “in- stance” names ina flattened versus a hierarchical mode, a context window (lower righthand window) that shows the current zoom area on the full chip layout, and a main viewing area that shows three windows con- taining different zoom perspectives of the same chip layout.

DECEMBER 1992 75

ETECHNOLOGY FOCUS: FPGA TOOLS

to distribute multiple clocks without introducing skew), design tools, may also have influenced the change in vendor. “Concurrent has a beautiful manual place-and-route program with a very good interactive editor,” says Minnis. “Up until now, Actel’s software has been push-button.”

About two months ago Concur- rent Logic also made an incremental design change, adding a feature to its pc-based CDS2100 Development System, which combines design en- try from Viewlogic (Marl- borough, MA) with propri- etary back-end tools. With the new feature, you can change a schematic that’s been completely or partially laid out, and im- plement the change in the layout without dis- turbing the existing placements and routes. By year’s end, Concur- rent will offer a Sun workstation interface, and by early next year CLi6000 designers will have the option of using Verilog and Synopsys (Mountain View, CA) syn- thesis.

Not wanting to be locked into a single FPGA vendor, especially one as new to the field as Concur- rent Logic, Larse is also buying silicon and tools from Xilinx (San Jose, CA). But Minnis is no booster of Xilinx place-and-route tools. “It’s really tricky to use Xil- inx’s interactive editor to move stuff around,” he believes.

Bl Specifying timing up front Xilinx began shipping a tool two months ago it says will significantly reduce the need to manually parti- tion and route critical portions of logic cell array (LCA) designs, elimi- nating three to five design iterations in the process. As part of Xilinx’s latest version of its XACT 4000 de- velopment system, the new XACT- Performance tool lets you enter your register transfer requirements (clock-to-setup), /o transfer require- ments (pad-to-setup and clock-to- output), and combinatorial logic re- quirements (pad-to-pad) in your schematics. The tool will inform you early if performance requirements are unrealistic for the design.

An early user of xact-Perform- ance, consultant Rocky Awalt, pres- ident of Highgate Design (Saratoga,

76 DECEMBER 1992 COMPUTER DESIGN

CA), relied on the new Xilinx soft- ware, which he refers to as deadline timing, to show engineers at client Boeing Aircraft (Renton, wA) why one of their 4005 LCAs wasn’t work- ing properly. Boeing designers are using dozens of Xilinx FPGAs on a 777 aircraft. “Before xact-Performance was available,” says Awalt, “Xilinx users complained about having to do a detailed analysis after compiling a design to determine whether or not the desired result had been

A Concurrent Logic FPGA user, senior project engineer Tom Minnis of Larse Corp uses the Concurrent interactive editor, Interact, to place and interconnect functional cells in a CLi6000 FPGA design destined for a T1 transmission product. “Concurrent’s software shows you all the possibilities,” reports Minnis.

achieved. The new software is quite powerful and will meet your timing specifications.”

About FPGA tools in general, and Xilinx tools in particular, Awalt says the routing delays and learning curve involved make it “nearly an oxymoron to speak about ease of use and perfor- mance at the same time. But there’s no such thing as a slow Xilinx LCA. There are just slow engineers.”

Senior design engineer Gene Jones at Universal Computing (San Diego, CA), a maker of bus boards and design consultants doing cus- tomer-driven designs, would proba- bly disagree with Awalt. Jones de- signed a Xilinx 3090 LCA into a multiprocessor board for the VMEbus and had to take it out and replace it with a QuickLogic (Santa Clara, CA) paAsic because the Xilinx part wouldn’t run at 20 MHz. “After you route a Xilinx part,” explains Jones, “you can have internal delays of hundreds of nanoseconds. I don’t have a person who can be a master of Xilinx tools. With QuickLogic, I don’t need an expert.”

Jones says he gets both perfor- mance and ease of use with Quick- Logic. “And with QuickLogic,” he adds, “there’s the predictability fac- tor. I can understand and predict what a part’s going to do, whereas with Xilinx, I don’t know until after place-and-route.” Just about the time Jones was giving up on the Xilinx 3090, Xilinx was introducing its 3100 family, which is pin- and software-compatible with 3000 parts and yet is up to twice as fast.

QuickLogic has sought to expand its customer base by enlisting third- party support. For the broad installed base of ABEL users, now number- ing over 30,000 PLD and FPGA designers world- wide, QuickLogic has partnered with Data vo (Redmond, WA), which de- veloped a device fitter for the pASIC 1 family. For designers wanting to stick with device-inde- pendent tools, Quick- Logic has shared technol- ogy with third-party NeocapD (Boulder, co), so that NeocaD’s FPGA Foun- dry can support the pAsic 1 family. FPGA Foundry also supports Xilinx devices.

A heavy user of FPGAs, Derek Rowe, CEO and chief engineer at Defence Products (Lower King- swoo, Surrey, U.K.), prefers to use FPGA Foundry rather than Xilinx tools to place and route the LCAs he designs into aircraft navigation sys- tems. “NeocaD is an order of magni- tude faster, and it’s right every time,” says Rowe, who’s now await- ing the second release of FPGA Foun- dry, which will include as an option a timing-driven tool called Timing Wizard. “This new tool will remove the need for manual iteration to achieve a maximum delay for a de- sign,” says Rowe, explaining that up until now designers have had to be conservative on the chip’s behalf be- cause of the unpredictability of tim- ing delays.

| Partitioning options open up

NeocaD announced a few weeks ago that the second release of its FPGA Foundry would also include an op- tional timing-driven tool called Prism, which provides automatic post-mapped partitioning of logic functions into multiple FPGAs. Un-

Selecting FPGA design tools

Becouce of the

advantages offered by programmable devices, many engi- neers are finding themselves design- ing their first FPGAS. As experienced us- ers will confirm, having the right tools is just as critical to this process as selecting the right device.

The right tools offer a minimum learn- ing curve, shorter design cycle, maxi- mum chip utilization and performance, and support for the device that's best suited to the design. The following guidelines will help FPGA designers select the proper tools for their needs.

B What makes a good toolset?

1) A good toolset should support the ex- isting CAE design environment. You should be able to use your existing cap- ture and simulation tools.

2) It should be complete. A minimum

toolset should include:

¢ Entry from all popular design methodologies (Palasm/aseL, sche- matic capture, VHDL), as well as transla- tors from industry standards such as EDIF and LPM.

¢ Mappers or fitters to convert your orig- inal design elements into the logic ele- - ments available in the selected FPGA.

* Device-specific optimization to provide efficient utilization of the logic within the FPGA without requiring you to man- ually perform device-specific optimiza- tion during design capture.

¢ Automatic placement and routing.

¢ A graphical editor with online design rule checking that can be used for pre- placing and routing critical signals, or debugging the design after the auto- matic tools have finished.

¢ Timing analysis, with the ability to compare the completed design against user-specified requirements and report back on potential problems.

e Automatic back-annotation of timing delays to the simulator of choice.

3) A toolset must deliver shorter time-to-

market. To make this a reality, the best

FPGA design tools:

¢ Keep the FPGA design cycle to the fewest iterations possible. This can be achieved using sophisticated algo-

rithms which converge on the best so- lution, and a rules-driven approach where requirements are set up front to reduce the amount of cleanup re- quired in the end.

¢ Provide the shortest time per iteration. This can be done by using fast-execut- ing algorithms, as well as the support of an incremental design capability where small changes don’t require a total relayout of the design.

4) The ability to optimize the perfor- mance and utilization of existing devices is essential. It's vital that the toolset pro- vides efficient optimization routines to best fit a design into the specific archi- tecture. Utilization and performance re- sults can vary considerably from fitter to fitter. Fortunately, the results are quantifia- ble, which lets you make comparisons easily through benchmarks.

5) The toolset should provide complete

control over itself and results. Auto-

mated solutions will only give satisfac-

tory results if you can truly direct the

tools. You should be able to:

¢ Specify preferences up front, with the tools adhering to these rules. Prefer- ences include physical constraints such as pin-outs and floorplanning, and tim- ing requirements such as clock fre- quencies, skew and path delays.

¢ Prioritize trade-offs. Tool developers constantly have to make decisions such as whether they need algorithm speed vs sophistication, with more complex algorithms requiring more time to execute.

6) It should have timing-driven capabili- ties. By specifying exact timing require- ments up front—frequency and path delays, and not just routing priority or critical versus non-critical—timing prob- lems can be eliminated before they even occur. As a result, timing-driven tools shorten the design cycle while providing significantly faster clock speeds. If for some reason the tools can’t meet the re- quirements automatically, they can pin- point exactly where the timing problem occurs, as opposed to the search-and- find tactics otherwise required.

7) Make designing FPGAS simple. To do this the tools must: Let you think in terms of your original

design methodology. An asic designer using an FPGA for prototyping, for ex- ample, shouldn't be required to de- sign as if the FPGA and not the Asic was the primary focus.

¢ Not require you to become an expert on the chip architecture to take full advan- tage of the device. This can be done us- ing a combination of powerful automatic tools to handle all but the most difficult or unusual design prob- lems, while letting you set requirements by specifying the desired result instead of detailing a specific implementation methodology (such as stating that the maximum path delay between registers isn't to exceed 20 ns, as opposed to “place the design in these logic blocks, route the nets in this order, and use these specific routing resources”).

8) Device independence is becoming in- creasingly important as FPGA vendors continue to enter the market and the tool must support this. Since each FPGA architecture has unique advantages and disadvantages, this trend is good for the user. You shouldn't have to buy and learn multiple sets of tools, however, to take advantage of newer devices which better fit your design requirements. In addition, tools should support the abil- ity to retarget existing designs.

9) Support of a technology-transparent

design methodology is also important.

This involves the ability to perform de-

sign capture and functional verification

independent of the final implementa-

tion technology (whether it be pcs, FPGA

or gate array). The tools should:

¢ Provide the ability to capture a design using generic libraries and attribute files, freeing designers from being locked into a specific architecture.